Qualcomm Incorporated

Texas Instruments Corporation

Rahul Gulati

Palkesh Jain

Alex Kwang Ho Jong

Mihir Narendra Mody

Andrew Evan Gruber

Donghyun Kim

Jay Chunsup Yun

Prashant Dinkar Karandikar

Brendon Lewis Johnson

Vasant Easwaran

Pranjal Bhuyan

Aishwarya Dubey

Jasbir Singh Nayyar

John Chi Kit Wong

Shashank Srinivasa Nuthakki

Nainala Vyagrheswarudu

Robert Hardacker

Nhon Toai Quach

Mohammad Reza Kakoee

Virendra Bansal

Anshuman Saxena

Dexter Tamio Chun

Niraj Nandan

Eric W Mahurin

Suresh Kumar Venkumahanti

Yanru Li

Mainak Biswas

Kedar Satish Chitnis

Roberto Avanzi

Ike Ikizyan

Rajat Sagar

Paul Christopher John Wiercienski

Jeffrey Hao Chu

Arun Shrimali

Kiran Kumar Malipeddi

Prithvi Y A Shankar

Sanjay Gupta

Peter Koster

Subrangshu Kumar Das

King Tam

Amit Aneja

Roberto Averbuj

Jeffrey Shabel

Sreekanth Modaikkal

Serafim Loukas, Jr

Nishi Bhushan Singh

Alex Jong

Arvind Jain

Dafna Shaool

Gary Arthur Ciambella

Hemang Jayant Shah

Kailash Digari

Sina Dena

Bipin Duggal

Kapil Bansal

Srinivas Kumar Vooka

Pranav Murthy

Hetul Sanghavi

Rakesh Kumar Kinger

Thomas Dannemann

Sriram Hariharan

Ratheesh Thekke Veetil

Vishwanath S

Dariusz Krolikowski

Shaowen Sun

Feng Zhou

Mattheus Heddes

David Barr

Edward Jacob Meisarosh

Reza Kakoee

This disclosure provides systems, methods, and devices for vehicles with automated driving systems. In a first aspect, a method of isolation in an automated driving system includes detecting the error in a first domain of the automated driving system, isolating a second domain of the automated driving system from the first domain, maintaining operation of the second domain after isolating the second domain from the first domain, and bypassing, by the second domain, the first domain to transmit notifications to an external controller via a first communication interface. Other aspects and features are also claimed and described.

Domain isolation in an automotive automated driving system

Various embodiments include components (e.g., a processor in a vehicle advanced driver assistance system) configured to identify subsystems that require testing in order to verify their compliance with a safety requirement. The components may determine whether verification of compliance requires that the subsystems be tested at PON, at POFF, during runtime or a combination thereof, dynamically determine the achievable parallelism for testing the identified subsystems, dynamically determine coverage level requirements for performing or executing built in self tests (BISTs) on each identified subsystem, and perform or execute the BISTs on the subsystems at the determined level of parallel and at the determined coverage level.

Dynamically re-configurable in-field self-test capability for automotive systems

An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.

Integrated circuit chip with cores asymmetrically oriented with respect to each other

Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors. In a second instance, the interfacing circuitry selectively communicates data bits along a first set of the number of conductors and error correction bits along a second set of the number of conductors.

Package on package memory interface and configuration with error code correction

The present disclosure relates to methods and apparatus for data processing, e.g., a display processing unit (DPU). The apparatus may receive data including a plurality of data bits, the data being associated with at least one data source. The apparatus may also determine whether at least a portion of the data corresponds to priority data, the priority data being within a region of interest (ROI). The apparatus may also detect an adjustment amount of the received data when at least a portion of the data corresponds to priority data, the data being displayed or stored based on the detected adjustment amount.

Methods and apparatus for data content integrity

In certain aspects, a device comprises a first processing unit; a first power distribution network coupled to the first processing unit; a first decoupling capacitor coupled to the first power distribution network; a second processing unit configured to be identical to the first processing unit; a second power distribution network coupled to the second processing unit; and a second decoupling capacitor coupled to the second power distribution network, wherein the second decoupling capacitor is configured to have different effect on the second power distribution network than the first decoupling capacitor on the first power distribution network.

Configurable redundant systems for safety critical applications

Various embodiments may include methods and systems for monitoring characteristics of a system-on-a-chip. Various embodiments may include inputting, from a test data input connection, test data to a first scan chain section including a first group of logic gates located within a first region of the SoC. Various embodiments may include providing, from a first clock gate associated with the first region of the SoC, a clock signal to the first group of logic gates. Various embodiments may include measuring, using a first sensor, the characteristics at a second region of the SoC in response to providing the clock signal to the first group of logic gates. Embodiments may further include processing or analyzing measured characteristics to determine a testing result.

In-field monitoring of on-chip thermal, power distribution network, and power grid reliability

The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.

Self-test during idle cycles for shader core of GPU

Systems, methods, and devices of the various embodiments enable dynamic configuration of a number of display regions of interest (ROIs) associated with safety critical content presented on a display, such as a vehicle display. Various embodiments may enable verification of data integrity for ROIs on a display. Various embodiments may enable the selection of different sets of display ROIs from a plurality of independent sets of display ROIs each associated with its own set of stored integrity check values (ICVs). Various embodiments may enable stored ICVs to be used to verify the data integrity of ROIs on a display. Various embodiments may enable the set of display ROIs and the associated ICVs for each display ROI to be changed after a number of frames have been displayed.

Dynamically re-configurable displays with reconfigurable regions of interest for safety critical content

In one embodiment, a system including a duty-cycle-monitoring circuit is configured to receive a monitored signal having cycles that have a high portion and a low portion. The duty-cycle-monitoring circuit includes: a cascade of buffers including a first buffer, wherein the first buffer is configured to receive a first signal based on the monitored signal, a plurality of corresponding flip-flops. Each flip-flop is triggered by a second signal based on the monitored signal. The data input of each flip-flop is connected to an output of a corresponding buffer. The duty-cycle-monitoring circuit further includes a control circuit configured to determine, based on a state of the plurality of flip-flops, a measure of the duration of the high portion of a cycle of the monitored signal and determine, based on a state of the plurality of flip-flops, a measure of duration of the low portion of a cycle of the monitored signal.

Digital duty-cycle monitoring of a periodic signal

Systems and method for error detection in automobile tell-tales are provided. An initial cyclic redundancy check (CRC) for a tell-tale to be calculated and stored at a primary control system within the vehicle. When a fault or condition is detected which generates the tell-tale, the primary control system passes video information to a display embedded control unit (ECU) along with the initial CRC. A circuit in the display ECU performs its own CRC calculation and compares the initial CRC to the calculated CRC. If there is not a match, then a fault indication may be provided to the primary control system for action by the primary control system. Still further, back up or fail-operational options may be invoked so that the tell-tale is provided to the operator.

Error detection in automobile tell-tales

Growing community of inventors

San Diego, CA, United States of America

Rahul Gulati