Intel Corporation

Rahul Bera

Sreenivas Subramoney

Belliappa Manavattira Kuttanna

Anant V Nori

Om Ji Omer

Shankar Balachandran

Avishaii Abuhatzera

Joydeep Rakshit

Apparatus and method for leveraging simultaneous multithreading for bulk compute operations. For example, one embodiment of a processor comprises: a plurality of cores including a first core to simultaneously process instructions of a plurality of threads; a cache hierarchy coupled to the first core and the memory, the cache hierarchy comprising a Level 1 (L1) cache, a Level 2 (L2) cache, and a Level 3 (L3) cache; and a plurality of compute units coupled to the first core including a first compute unit associated with the L1 cache, a second compute unit associated with the L2 cache, and a third compute unit associated with the L3 cache, wherein the first core is to offload instructions for execution by the compute units, the first core to offload instructions from a first thread to the first compute unit, instructions from a second thread to the second compute unit, and instructions from a third thread to the third compute unit.

Method and apparatus for leveraging simultaneous multithreading for bulk compute operations

Growing community of inventors

Zürich, Switzerland

Rahul Bera