Texas Instruments Corporation

Pinterest, Inc.

Microsoft Technology Licensing, LLC

Adobe, Inc.

Samsung Electronics Co., Ltd.

Qualcomm Incorporated

Hewlett-Packard Development Company, L.p.

Arista Networks, Inc.

Rahul Anand Sharma

Sandeep Kesrimal Oswal

Jagannathan Venkataraman

Jurij Leskovec

Chantat Eksombatchai

Mark Bormann Ulrich

Prasanth K

Srinivasa Rao Madala

Charles Walsh Sugnet

Ranveer Chandra

Visvesvaraya Appala Pentakota

Eeshan Miglani

Rakul Viswanath

Karthikeyan Gunasekaran

Ankit Tripathi

Tridib Roy Chowdhury

Adarsh Ghagta

Rajashekar Goroju

Dileepkumar Ramesh Bhat

Jaiganesh Balakrishnan

Sriram Murali

Sarma Sundareswara Gunturi

Sthanunathan Ramakrishnan

Nagarajan Viswanathan

Tusher Chakraborty

Nagesh Surendranath

Zerina Kapetanovic

Nishanth Chandran

Aswath Vs

Rajshekhar Biradar

Vajeed Nimran

Sravana Kumar Goli

Rahul Kumar Singh

Ram Narayan Krishna Nama Mony

Anamika Sharma

Rakesh Chikkanayakanahalli Manjunath

Nagesh Narayana Swamy

Divya Gupta

Manohar Swaminathan

Puranjaya Pradhan

Akshay Uttama Nambi Srirangam Narashiman

Jonathan Appavoo

Pranav Jindal

Prasad Gandewar

Zitao Liu

Yovan Sethi

Aswath V S

Snehasish Roychowdhury

Sarma Sudareswara Gunturi

Deepak Muddegowda

Mayank Rathee

Nishant Kumar

Amar Kumar

Deevashwer Rathee

Krishna Kishor Jha

Abhishek Avasthi

Aseem Rastogi

A secure inference over Deep Neural Networks (DNNs) using secure two-party computation to perform privacy-preserving machine learning. The secure inference uses a particular type of comparison that can be used as a building block for various layers in the DNN including, for example, ReLU activations and divisions. The comparison securely computes a Boolean share of a bit representing whether input value x is less than input value y, where x is held by a user of the DNN, and where y is held by a provider of the DNN. Each party computing system parses their input into leaf strings of multiple bits. This is much more efficient than if the leaf strings were individual bits. Accordingly, the secure inference described herein is more readily adapted for using in complex DNNs.

Private inference in deep neural network

An integrated circuit including a comparator having an enable signal input and an output and timing circuitry. The timing circuitry includes a first transistor having a control terminal, a second transistor having a control terminal, a first inverter having an input coupled to the control terminal of the second transistor and having an output coupled to the enable signal input, and a second inverter having an input coupled to the output of the comparator and having an output coupled to the control terminal of the first transistor.

Asynchronous analog-to-digital converter

This disclosure describes systems and methods that facilitate the generation of recommendations by traversing a graph. Walks that traverse the graph may be initiated from a plurality of different nodes in the node graph. In order to give greater or lesser weight to particular nodes, the walks may have different lengths depending on the nodes from which they are initiated, or an unequal amount of walks may be distributed between nodes from which walks are initiated. A plurality of walks through a node graph may be tracked, and visit counts or scores for nodes in the node graph may be determined. For example, scores may be increased for nodes that are visited by a walk initiated from a first node and a second walk initiated from a second node, or scores may be decreased for nodes that are not visited by a first walk initiated from a first node and a second walk initiated from a second node. Content corresponding to nodes may be recommended based on the scores or visit counts.

Node graph pruning and fresh content

An example apparatus includes: controller circuitry configured to: provide switch signals to capacitive digital to analog converter (C-DAC) circuitry, the C-DAC circuitry including switches; configuring the switches into a third configuration begin an Auto Zero (AZ) phase with a third switch in a closed state; configuring the switches into a fourth configuration to repeat the transition of the third switch to the open state corresponding to a first configuration; configuring the switches into a fifth configuration to repeat the transition of a first switch and a second switch to the open state corresponding to a second configuration; configuring the switches into a sixth configuration to repeat the transition of the third switch to the closed state corresponding to a second configuration; and performing an AZ decision with the switches in the sixth configuration.

Methods and apparatus to capture switch charge injections and comparator kickback effects

An example analog-to-digital converter (ADC) comprising: sample and hold circuitry coupled to an analog input; a first sub-ADC coupled to the sample and hold circuitry; a multiplying digital-to-analog converter (M-DAC) coupled to the first sub-ADC; summation circuitry coupled to the sample and hold circuitry and the M-DAC; an amplifier coupled to the summation circuitry; a second sub-ADC coupled to the amplifier; and reference generation circuitry coupled to the first sub-ADC, the M-DAC, and the second sub-ADC, the reference generation circuitry including: reference voltage circuitry coupled to the M-DAC; a first resistor coupled to the reference voltage circuitry; a second resistor coupled to the first resistor; and a capacitor coupled in parallel to the second resistor by a switch.

Methods and apparatus to reduce inter-stage gain errors in analog-to-digital converters

A pull-print server may include a receiver to receive a print job from a client device. The print job includes a first page and a second page. Further, the pull-print server may include a transmitter to transmit the print job to a printer via a network in response to a reception of a first pull-print request from the printer. The pull-print server may include a controller to receive page count information from the printer upon completion of printing of the first page. The page count information indicates a number of pages printed corresponding to the print job. Further, the controller may detect an interruption of the print job prior to completion of the print job and cause the interrupted print job to resume on the printer based on the page count information and in response to a reception of a second pull-print request from the printer.

Pull-print servers

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for a smart compositor module. A display processor may obtain a plurality of layers associated with at least one frame in a scene. The display processor may identify a composition capability of a first portion of at least one DPU and a second portion of the at least one DPU. The display processor may allocate at least one first layer of the plurality of layers to the first portion of the at least one DPU and at least one second layer of the plurality of layers to the second portion of the at least one DPU. The display processor may compose the at least one first layer at the first portion of the at least one DPU and the at least one second layer at the second portion of the at least one DPU.

Smart compositor module

A low noise amplifier for an RF sampling analog front end. The amplifier includes digital step attenuation for applying a selected attenuation to signals received at an input node, and a gain stage coupled to amplify the attenuated signal from the digital step attenuation circuit. In a differential amplifier implementation, a first input capacitor is coupled between a positive side input node and an output of the negative side digital attenuation circuit, and a second input capacitor is coupled between a negative side input node and an output of the positive side digital step attenuation circuit. In some embodiments, variable feedback circuits are coupled between each input node and an output of the corresponding gain stage, to selectively apply active termination at the input at high gain settings of the amplifier. Variable input and output resistors, and programmable noise filtering at the output, are provided in some embodiments.

Programmable gain low noise amplifier

A spur correction system for a transmit chain having an interleaving multiplexer. In some embodiments, the spur correction system includes a spur sense chain, a correction controller, and a Q path corrector. The interleaving multiplexer combines signals from multiple bands in response to a clock signal. The spur sense chain estimates an error that is in phase with the clock signal (an I-phase error) and an error that is a derivative of the clock signal (a Q-phase error). The correction controller compensates for the estimated I-phase error by injecting an I-phase correction signal into the transmit chain. The Q path corrector compensates for the estimated Q-phase error by selectively connecting one or more capacitors within the interleaving multiplexer.

F/2 spur estimation and correction

Systems and methods are provided herein for transitioning a supplicant from one virtual local area network (VLAN) to another using a change of authorization (COA) message. This may be accomplished by an authentication server notifying a network device that a host should be granted access to the network, wherein the authentication server authenticates the host using MAC based authentication. Based on this notification and the MAC address of the host, the network device assigns the host to a first VLAN. If the authentication server determines that the host needs to change from the first VLAN to a second VLAN the authentication server generates a COA message, associated with the host, wherein the COA message comprises a VLAN identifier related to the second VLAN. The authentication server transmits the COA message to the network device causing the network device to route traffic to and from the host using the second VLAN.

Systems and methods for changing a supplicant from one virtual local area network to another using a change of authorization message

Methods, systems, and non-transitory computer readable storage media are disclosed for training a machine-learning model utilizing batchwise weighted loss functions and scaled padding based on source density. For example, the disclosed systems can determine a density of words or phrases in digital content from a digital content source that indicate an affinity towards one or more content classes. In some embodiments, the disclosed systems can use the determined source density to split digital content from the source into segments and pad the segments with padding characters based on the source density. The disclosed systems can also generate document embeddings using the padded segments and then train the machine-learning model using the document embeddings. Furthermore, the disclosed system can use batchwise weighted cross entropy loss for applying different class weightings on a per-batch basis during training of the machine-learning model.

Training digital content classification models utilizing batchwise weighted loss functions and scaled padding based on source density

A radio frequency transmitter includes an upconverter that outputs in-phase (I) and quadrature (Q) signals, a digital timing offset circuit, first and second digital-to-analog converters (DACs), an analog timing offset removal circuit, first and second pulse shapers, and an adder. The digital timing offset circuit introduces a time offset between the I and Q signals. The first and second DACs output analog I and Q signals, respectively, and have first and second clock signals, respectively. The first and second clock signals have the same frequency and are offset relative to each other by the time offset. The analog timing offset removal circuit removes the time offset between the analog I and Q signals. The first and second pulse shapers receive the analog I and Q signals, respectively, and output pulse-shaped I and Q signals. The adder receives the pulse-shaped I and Q signals and outputs an intermediate frequency signal.

Low intermediate frequency transmitter

A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

Radio-frequency digital-to-analog converter system

Systems, methods, and non-transitory computer-readable media are disclosed for utilizing focused aggregation of classification model outputs to classify variable length documents. For instance, the disclosed systems can utilize a classification model to determine category scores for segments from an electronic document. Furthermore, the disclosed systems can identify positive trigger segments from the segments by comparing the category scores to a threshold category score. Moreover, the disclosed systems can determine a positive trigger ratio for the target category based on the positive trigger segments and the segments. Additionally, the disclosed systems can generate an aggregated category score for the electronic document from the positive trigger segments (when the positive trigger ratio satisfies a threshold positive trigger ratio) and distribute the electronic documents to client devices based on the aggregated category score.

Focused aggregation of classification model outputs to classify variable length digital documents

Growing community of inventors

Alwar, India

Rahul Anand Sharma