Arm Limited

Rahoul Kumar Varma

David Francis McHale

Gareth Duncan

Marc Richard Wicks

Mike Livesley

Philippe Jean-Pierre Raphalen

Kinjal Dave

Saran Kumar Seethapathi

Roma Kundu

Christophe Justin Evrard

A data processing apparatus and method has a plurality of processing units, at least one of which is configured to be switchable between an active power state and a dormant power state and the units share a memory, and at least one local storage unit is configured to store a local copy of a data item stored in the memory for access by an associated processing unit. A snoop control unit is monitors memory access requests and when one is issued, if the control unit has an indication that a local storage unit belonging to another dormant processing unit has a local copy of that data storage item and a cache coherency protocol required that the local copy of the requested data item associated with the other processing unit be invalidated, the control unit stores a marker indicating that that other local copy should later be invalidated.

Handling of memory access requests to shared memory in a data processing apparatus

A data processing apparatus is provided, which is operable to access data values associated with a respective address values. The data processing apparatus has: a processor; a main memory having a secure data values region; a cache; and cache interface logic having data transaction logic and security determination logic. The data transaction logic receives from the processor a data access request for accessing data in cache. The data access request has an associated address value and a security attribute. If the security attribute indicates that the request is a non-secure data-access request, the security determination logic determines, via a data region allocation table, whether the request is associated with the secure data values region of main memory and the non-secure data access request is allowed to complete if it is not associated with the secure data region.

Data processing apparatus security

A data processing apparatus and a method for caching data values in data processing apparatus comprising a level one cache and a level two cache is disclosed. Both the level one cache and the level two cache are operable to store the data values. The method comprises the steps of: a) receiving a transaction request in which a data transaction relating to a data value is requested to occur, the transaction request including cache policy attributes associated with an address of the data value; and b) determining from the cache policy attributes whether or not the data value can be stored by the level one cache and the level two cache and, if so, in which one of the level one cache and the level two cache the data value is to be stored in order to ensure that the data value is prevented from being stored in both the level one cache and the level two cache. Providing cache policy attributes with each data transaction enables a simple determination to be made of which cache should be used to store each data value, with other caches being prevented from storing that data value. Such an approach obviates the need to perform any complex operations in order to determine which cache should be used to store that data value. Hence, a data value may be prevented from being stored in both the level one cache and the level two cache at any one time which ensures that the level one cache and level two cache do not store duplicate data thereby increasing the likelihood of a cache hit within level one or level two for any data value.

Caching data

The present invention provides a data processing apparatus and method for storing trace data. The data processing apparatus comprises a bus operable to interconnect a number of master devices and slave devices to enable transactions to be routed between the master and slave devices. Each master device is able to initiate a transaction, with the transaction specifying a transaction address. A cache is interposed between at least one of the master devices and the bus and is operable to receive the transaction issued by that master device. The cache has a cache memory and a cache controller operable to control access to the cache memory. The cache controller comprises caching logic operable to selectively cache a data value of the transaction at a location in the cache memory chosen dependent on the transaction address. Control storage is provided identifying a trace address range specifying a trace region. Further, trace logic is provided which is operable to selectively generate as trace data one or more attributes associated with the transaction and to provide in association with that trace data a trace address selected from the trace address range. The caching logic is then operable to store the trace data at a location in the cache memory chosen dependent on the trace address. In this way, the cache can be used in a flexible manner to not only act as a normal cache but also to selectively store within the cache trace data.

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Berkshire, United Kingdom

Rahoul Kumar Varma