Intel Corporation

Rahima K Mohammed

Ridvan A Sahan

Prabhakar Subrahmanyam

Ying-Feng Pang

Yi Xia

Victor Polyanko

David W Grawrock

Pooya Tadayon

Jun Lu

Bruce Querbach

Tieyu Zheng

Keshavan K Tiruvallur

Mark B Trobough

Chinna B Prudvi

Vui Yong Liew

Hermann Gartler

Ashok N Kabadi

Samie B Samaan

Keith A Drescher

Mukesh Kataria

Jay Joseph Nejedlo

Lyle E Cool

Arun Krishnamoorthy

James J Grealish

Russell J Wunderlich

Mustafa H Haswarey

Brian Meyer

Abhijit Davare

Tong Wa Chao

Priyadarsan Patra

Guoliang Ying

William Penner

Liguang Du

John L Baudrexl

Arun R Ramadorai

Kapila B Udawatta

Wee Hoo Cheah

Guangying Zhang

Yuen Tat Lee

Kyle Markley

Christian E Iovin

Aslam H Haswarey

Loren James McConnell

Kip C Killpack

Timothy S Storey

Yi Amy Xia

Edwin E Parks

Padmakumar Gopal

Sanjay S Salem

David C Florey

Travis K Goff

Evan J Halprin

Jiun Long Foo

Selvakumar Raja Gopal

Chuanlou Wang

Peng Wei

Xiang Que

Muhammad Ahmad

Neil Dobler

Nagib Z Hakim

Techniques for heat sinks and cold plates for compute systems are disclosed. In one embodiment, a heat sink includes two sub-heat sinks that are mechanically connected but thermally isolated. The two sub-heat sinks can independently cool different dies on the same integrated circuit component. In another embodiment, a system includes an integrated circuit component that is cooled by a first water block and a second water block. The first water block forms a loop with a gap in it, and the second water block has a pedestal that extends through the gap in the first water block to contact the integrated circuit component. The first water block and the second water block can independently cool different dies on the same integrated circuit component.

Technologies for isolated heat dissipating devices

An apparatus is described. The apparatus includes a liquid cooling system having multiple heat-exchangers and multiple valves. The multiple valves are to enable/disable participation of individual ones of the heat-exchangers within the liquid cooling system. The apparatus includes an information keeping device to store information that correlates a number of the multiple heat exchangers to be enabled to realize one or more semiconductor chips' target temperature for a power consumption of the one or more semiconductor chips for a plurality of combinations of target temperature and power consumption. The controller is coupled to the liquid cooling system and the information keeping device to dynamically determine during runtime of a system having the one or more semiconductor chips an appropriate number of the multiple heat exchangers to enable to realize a particular target temperature for the one or more semiconductor chips for a particular power consumption of the one or more semiconductor chips, and, update the information in the information keeping device with a new correlation that correlates the appropriate number with the particular target temperature and particular power consumption.

Self cooling adaptive flow branching heat exchanger system for cooling of one or more semiconductor chips

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

The present description relates to the field of microelectronic device retention mechanisms and, more particularly, to a quick release retention mechanism including a base plate, a load plate and a biasing mechanism adapted to apply a desired load and to allow rapid insertion and extraction of microelectronic devices from sockets.

Quick release retention mechanism for socketed microelectronic devices

Growing community of inventors

San Jose, CA, United States of America

Rahima K Mohammed