Wilinx Corporation

Microchip Technology Inc.

Rahim Bagheri

Masoud Djafari

Edris Rostami

Ahmad Mirzaei

Mohammad E Heidari

Mahdi Bagheri

Abbas Komijani

Alireza Mehrnia

Omid Rajaee

Jun Wang

Esmael Heidari

Mohammad Mehrjoo

Filipp A Baron

Mohsen Pourkhaatoun

Saeed Pourbagheri

Edwin Chiem

Hamid Shafiee

Ali Fard

Siddharth Shetty

Kiran Gowda

Kaveh Moazzami

Alireza Tarighat-Mehrabani

Ali Karimi-Sanjaaani

Mahmoud Darvishzadeh

Mike Choi

Mahnaz Atri

Delta-sigma modulation utilizing continuous-time input and discrete-time loop filter. An apparatus includes an input circuit, a switched-capacitor, an integrator, a quantizer and a feedback loop. The input circuit receives an analog signal and produce an analog input signal, the input circuit comprising a resistor-capacitor (RC) integrator. The switched-capacitor samples the analog input signal and produce a discrete-time, sampled input signal. The integrator processes the discrete-time, sampled input signal. The quantizer converts an output of the integrator to a digital signal. The feedback loop provides the digital signal to respective inputs of the RC integrator and the integrator.

ΔΣmodulation utilizing continuous-time input and discrete-time loop filter

Embodiments of the present disclosure include an OFDM receiver circuit, which includes an FFT circuit configured to calculate an FFT of a plurality of sample values received by the receiver circuit, and a smoothing circuit configured to identify equalizer coefficients for the sample values by truncating portions of an impulse response of the FFT.

Channel estimation in OFDM communication systems

Various embodiments relate to delta-sigma loop filters with input feedforward. A delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. The delta-sigma loop filter may further include a first summing node having an output coupled to an input of the first integrator. Further, the delta-sigma loop filter may include a feedforward path from an input of the delta-sigma loop filter to a first input of the first summing node. The delta-sigma loop filter may also include a first feedback path from an output of the quantizer to a second input of the first summing node.

Delta-sigma loop filters with input feedforward

Various embodiments relate to an analog-to-digital converter (ADC). The ADC may include a first channel including a first delta-sigma loop filter and a second channel including a second delta-sigma loop filter. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may also include a first summing node having an output coupled to an input of the first integrator, and a feedforward path from an input of the delta sigma loop filter to a first input of the first summing node. Further, each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first feedback path from an output of the quantizer to a second input of the first summing node.

Programmable receivers including a delta-sigma modulator

A receiver circuit includes a conversion circuit configured to down-convert a received radio-frequency signal to a baseband signal, an analog-to-digital converter configured to sample the baseband signal into a sampled signal, a Fast Fourier transform (FFT) circuit configured to perform an FFT on the sampled signal, and a digital compensation circuit configured to compensate for IQ distortion in a frequency domain.

Digital compensation of IQ coupling in communication receivers

Embodiments of the present invention include methods for wide bandwidth synthesizer circuits and methods. In one embodiment, the present invention includes a frequency synthesizer comprising a multiplexer and a band group selector. The multiplexer is coupled to receive a plurality of sinusoidal signals. Each sinusoidal signal has a unique frequency. The band group selector selects between a plurality of band groups. The band group selector is coupled to receive a first signal from the multiplexer. The multiplexer multiplexes between the plurality of sinusoidal signals and provides the first signal. The band group selector includes a band mixer. The band mixer mixes the first signal with a band signal having a band frequency. The band signal corresponds to a band group selected from the plurality of band groups. The band group selector provides a transmitter mixer signal and a receiver mixer signal.

Wide bandwidth fast hopping frequency synthesizer circuits and methods

Embodiments of the present invention include circuits and methods for improving the spectral purity of mixer circuits. In one embodiment the present invention includes a mixer circuit comprising a first transistor having a gate, a source and a drain, a second transistor having a gate, a source and a drain, a first capacitance coupled between the source of the first transistor and the source of the second transistor and a bias circuit having an input, a first output coupled to the source of the first transistor and a second output coupled to the source of the second transistor. The present invention may be advantageously used in a wireless transmitter application.

Mixer circuits and methods

Embodiments of the present invention include programmable filter circuits and methods. In one embodiment, the present invention includes a programmable filter for filtering an input signal comprising a storage element for storing a plurality of digital values representing a discrete time window function, and a plurality of filter channels, each channel comprising a multiplying digital-to-analog converter having a plurality of digital inputs coupled to the storage element and an analog input for receiving said input signal to be filtered, at least one capacitor having at least one terminal coupled to an output of the multiplying digital-to-analog converter, and a sampling device coupled between the at least one terminal of the at least one capacitor and an output of the filter. In another embodiment, the present invention includes a software defined radio.

Programmable filter circuits and methods

Embodiments of the present invention transmit signals simultaneously over a communication channel at different RF center frequencies, and may use a single power amplifier and antenna. In one embodiment the present invention includes a method of transmitting information in a wireless communication channel comprising receiving digital signals having data to be transmitted, converting the signals to analog signals, up-converting each analog signal, combining the up-converted signals, amplifying the combined up-converted signal and transmitting the combined up-converted signal. In one embodiment, the same data is sent over a transmission channel at two different frequencies to improve reliability.

Wireless communication systems and methods

In one embodiment, the present invention includes an electronic circuit comprising a first stage having a first differential inductive element and a second differential inductive element, and a second stage coupled to an output of the first stage, the second stage having a first differential inductive element and a second differential inductive element, wherein the first and second differential inductive elements of the first stage couple magnetically to generate a first phase error, wherein the first and second differential inductive elements of the second stage couple magnetically to generate a second phase error, and wherein the second phase error cancels the first phase error.

Phase error cancellation for differential signals

Embodiments of the present invention include circuits and methods with wide bandwidths. In one embodiment, parasitic capacitances of the output of a first stage and the input of a second stage are included in a network. The output of the first stage is coupled to the input of the network, and the input of the second stage is coupled to an intermediate node of the network. In one embodiment, the parasitic capacitance of the second stage is the largest capacitance in the network. In another embodiment, passive networks are coupled to the outputs of a stage, and one or more current injection circuits may be used to extend the bandwidth of the circuit.

Wideband circuits and methods

Embodiments of the present invention include a frequency synthesizer comprising a first plurality of dividers receiving a first signal having a first frequency and generating a first plurality of divided signals and a frequency combination network including a plurality of mixers, the frequency combination network receiving one or more of the first plurality of divided signals and generating a plurality of synthesized signals having different frequencies. The frequency combination network may further include additional dividers and multiplexers for more flexibility in synthesizing different frequencies. In one embodiment, the frequency combination network is coupled to dividers in the feedback path of a phase locked loop. The present invention is particularly advantageous for synthesizing frequencies above one (1) gigahertz.

High frequency synthesizer circuits and methods

Embodiments of the present invention include circuits and methods for reducing DC Offset. In one embodiment the present invention includes storing DC offset on internal capacitances. In one embodiment, parallel stages are used to remove DC offset corresponding to different local oscillator frequencies. Embodiments of the invention further include changing the low cutoff frequency of the DC cancellation circuits for fast calibration. In a first state, a high pass filter may have a first low cutoff frequency, and in a second state the high pass filter may have a second cutoff frequency lower than the first low cutoff frequency. The present invention also includes a variable gain amplifier with reduced DC offset.

DC offset cancellation circuits and methods

Embodiments of the present invention include circuits and methods for dividing signals. In one embodiment the present invention includes a divider circuit comprising at least one first divider input receiving an in-phase (I+) signal, at least one second divider input receiving a complement of the in-phase (I&#x2212;) signal, at least one third divider input receiving a quadrature (Q+) signal, and at least one fourth divider input receiving a complement of the quadrature (Q&#x2212;) signal. In one embodiment, the lock range of a divider is improved by providing a first bias current greater than a second bias current.

Divider circuits and methods using in-phase and quadrature signals

Embodiments of the present invention include circuits and methods with wide bandwidths. In one embodiment, parasitic capacitances of the output of a first stage and the input of a second stage are included in a network. The output of the first stage is coupled to the input of the network, and the input of the second stage is coupled to an intermediate node of the network. In one embodiment, the parasitic capacitance of the second stage is the largest capacitance in the network.

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Los Angeles, CA, United States of America

Rahim Bagheri