Samsung Electronics Co., Ltd.

Raheel Azmat

Chul-hong Park

Chulhong Park

Kwanyoung Chun

Deepak Sharma

Rwik Sengupta

Jinwoo Jeong

Sang-jun Park

Jae-Seok Yang

Kwan-Young Chun

Hyun-jong Lee

Sidharth Rastogi

Taehyung Kim

Sharma Deepak

Su-Hyeon Kim

Subhash Kuchanuri

Jiwook Kwon

Pan-Jae Park

Sengupta Rwik

Jae-Hyoung Lim

Jaeseok Yang

Jaehyoung Lim

An integrated circuit including a standard cell includes: a plurality of first wells extending in a first horizontal direction with a first width and of a first conductivity type; and a plurality of second wells extending in the first horizontal direction with a second width and having a second conductivity type, wherein the plurality of first wells and the plurality of second wells are alternately arranged in a second horizontal direction that is orthogonal to the first horizontal direction, and when m and n are integers greater than or equal to 3, the standard cell has a length in the second horizontal direction, the length being equal to a sum of m times a half of the first width and n times a half of the second width.

Integrated circuit including standard cell and method of fabricating the integrated circuit

A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.

Semiconductor device

A semiconductor integrated circuit includes a substrate, and a standard cell on the substrate. The standard cell includes a first wiring structure electrically connecting a first gate pattern to a fourth gate pattern, and a second wiring structure electrically connecting a second gate pattern to a third gate pattern. The first wiring structure includes a first lower wiring layer, a second lower wiring layer, first and second intermediate wiring layers, and a first upper wiring layer. The second wiring structure includes a third lower wiring layer, a fourth lower wiring layer, third and fourth intermediate wiring layers, and a second upper wiring layer.

Semiconductor integrated circuit

Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

Integrated circuit and standard cell library

A scan flip-flop includes a multiplexer, a first latch, a second latch, an output buffer and a clock buffer. The multiplexer selects one of a data input signal and a scan input signal based on an operation mode. The first latch latches an output of the multiplexer. The second latch latches an output of the first latch. The output buffer generates an output signal based on an output of the second latch. The clock buffer generates a first clock signal and a second clock signal that control operation of the first latch and the second latch. The first latch, the second latch, and the clock buffer are sequentially arranged along a first direction. A first clock line supplying the first clock signal and a second clock line supplying the second clock signal have a cross couple connection.

Scan flip-flop, flip-flop and scan test circuit including the same

An integrated circuit device includes a substrate including a fin active region extending in a first direction, a gate line intersecting the fin active region and extending in a second direction perpendicular to the first direction, a power line electrically connected to source/drain regions at sides of the gate line on the fin active region, a pair of dummy gate lines intersecting the fin active region and extending in the second direction, and a device separation structure electrically connected to the pair of dummy gate lines and including a lower dummy contact plug between the pair of dummy gate lines on the fin active region and electrically connected to the power line, and an upper dummy contact plug on the lower dummy contact plug and on the pair of dummy gate lines to electrically connect the lower dummy contact plug to the pair of dummy gate lines.

Integrated circuit devices

Integrated circuit devices and method of manufacturing the same

Provided is a semiconductor device including a substrate with first, second, and third logic cells, active patterns provided in each of the first to third logic cells to protrude from the substrate, and gate structures crossing the active patterns. The second and third logic cells are spaced apart from each other in a first direction with the first logic cell interposed therebetween. The active patterns are arranged in the first direction and extend in a second direction crossing the first direction. When measured in the first direction, a distance between the closest adjacent pair of the active patterns with each in the first and second logic cells respectively is different from that between the closest pair of the active patterns with each in the first and third logic cells respectively.

A logic semiconductor device includes a plurality of active patterns extending in a horizontal direction and being spaced apart from each other in a vertical direction, an isolation layer defining the active patterns, a plurality of gate patterns extending in the vertical direction on the active patterns and the isolation layer, the gate patterns being spaced apart from each other in the horizontal direction, a plurality of lower wirings extending in the horizontal direction over the gate patterns, a plurality of upper wirings extending in the vertical direction over the lower wirings, a through contact connecting at least one upper wiring of the upper wirings and at least one gate pattern of the gate patterns, the through contact extending from a bottom surface of the upper wiring to a position under a bottom surface of one of the lower wirings relative to the active patterns.

Logic semiconductor devices

An integrated circuit includes at least one cell. The at least one cell includes a cell region defined by a cell boundary; a power line structure extending in a first direction parallel to and along the cell boundary and including a first power line extending in the first direction along the cell boundary, a plurality of metal islands spaced apart from one another over the first power line in the first direction, and a second power line extending in the first direction over the plurality of metal islands; and a signal line structure disposed in the cell region at the same level as the first power line and the plurality of metal islands. Separation distances between each of the plurality of metal islands and a part of the signal line structure at the same level as the plurality of metal islands are equal to or greater than a critical separation distance.

Growing community of inventors

Suwon-si, South Korea

Raheel Azmat