Sandisk Technologies Inc.

Sandisk 3d LLC

Rensselaer Polytechnic Institute

Pohang University of Science and Technology Foundation

Raghuveer S Makala

Rahul Sharangpani

Fei Zhou

Senaka Kanakamedala

Adarsh Rajashekhar

Yao-Sheng Lee

Yanli Zhang

Johann Alsmeier

George Matamis

Sateesh Koka

Ramy Nashed Bassely Said

Peter Rabkin

Somesh Peri

Ashish Kumar Baraskar

Jayavel Pachamuthu

Seung-Yeul Yang

James K Kai

Murshed Chowdhury

Jin Liu

Keerti Shukla

Henry Chien

Franz Kreupl

Wei Zhao

Masanori Tsutsumi

Naoki Takeguchi

Fumitaka Amano

Monica Titus

Masaaki Higashitani

Steven J Radigan

Vance Dunton

Deepak Chandra Sekar

Yung-Tin Chen

Bhagwati Prasad

Michael Konevecki

Peng Zhang

Zhenyu Lu

Kensuke Yamaguchi

Srikanth Ranganathan

Genta Mizuno

Paul Wai Kie Poon

Yusuke Mukae

Natalie Nguyen

Yingda Dong

Jiahui Yuan

Hiroyuki Kinoshita

Zhixin Cui

Xiying Costa

Chun Ge

Masanori Terahara

Yujin Terasawa

Jian Feng Chen

Christopher John Petti

Ching-Huang Lu

April Dawn Schricker

Tatsuya Hinoue

Michiaki Sano

Akio Nishida

Seiji Shimabukuro

Thomas Jongwan Kwon

Daxin Mao

Jingyan Zhang

Atsushi Suyama

Shigehisa Inoue

Tiffany Santos

Tomoyuki Obu

Junichi Ariyoshi

Hiroyuki Ogawa

Dana Lee

Tuan Duc Pham

Klaus Florian Schuegraf

George Samachisa

Tong Zhang

Michael L Chan

Takashi Whitney Orimoto

Wipul Jayasekara

Liang Pang

Wu-Yi Henry Chien

Steven Patrick Maxwell

Andrew C Lin

Kiyohiko Sakakibara

Abhijit Bandyopadhyay

Jixin Yu

Koichi Matsuno

Xiying Chen

Naohiro Hosoda

Kun Hou

Yoichiro Tanaka

Xue Bai Pitner

Kengo Kajiwara

Tadashi Nakamura

Lin Hou

Chu-Chen Fu

Matthias Baenninger

Tomohiro Kubo

Shigehiro Fujino

Ryo Nakamura

Kazuto Watanabe

Wenguang Shi

Marika Gunji-Yoneoka

Yusuke Ikawa

A first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers is formed over a substrate. A first-tier memory opening is formed, and is filled with a first-tier sacrificial memory opening fill structure. A second-tier alternating stack of second-tier insulating layers and second-tier sacrificial material layers is formed. An etch mask layer is formed, and a second-tier memory opening is formed through the second-tier alternating stack. An etch mask removal process is performed which collaterally removes a top portion of the first-tier sacrificial memory opening fill structure. A sacrificial pillar structure is formed by performing a selective material deposition process. An inter-tier memory opening is formed by removing the first-tier sacrificial memory opening fill structure and at least a central portion of the sacrificial pillar structure. A memory opening fill structure is formed, and the sacrificial material layers are replaced with electrically conductive layers.

Three-dimensional memory device and method of making thereof using sacrificial material regrowth

A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a first etch mask material layer, forming a first cladding liner, and forming a via opening through the alternating stack by performing an anisotropic etch process that employs a combination of at least the first cladding liner and the first etch mask material layer as a composite etch mask structure.

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings. Each of the memory opening fill structures includes a vertical stack of memory elements located at levels of the electrically conductive layers. Each of the electrically conductive layers includes a metallic barrier liner containing an intermetallic compound of at least two elements that includes a first metal element including Ta or Ti, and a second metal element including at least one of Al or Mo, and metallic barrier liner containing less than 10 atomic percent of nitrogen and oxygen, and a metallic fill material layer contacting the metallic barrier liner.

Three-dimensional memory device with intermetallic barrier liner and methods for forming the same

A memory device includes a first electrically conductive line laterally extending along a first horizontal direction, a memory pillar structure overlying and contacting the first electrically conductive line, the memory pillar structure includes a vertical stack of a ferroelectric material plate and a selector material plate, and a second electrically conductive line laterally extending along a second horizontal direction and overlying and contacting the memory pillar structure.

Bonded memory devices and methods of making the same

A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

Memory device containing composition-controlled ferroelectric memory elements and method of making the same

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory elements, and a first backside trench fill structure and a second backside trench fill structure. Each of the electrically conductive layers includes a respective metal nitride liner and a respective metal fill material region. The respective metal fill material region includes a respective first-thickness portion having a respective first vertical thickness and a respective second-thickness portion having a respective second vertical thickness that is greater than the respective first vertical thickness.

Three-dimensional memory device containing variable thickness word lines with reduced length metal nitride diffusion barriers and methods for forming the same

A semiconductor structure includes a doped single crystalline semiconductor material layer, a metal or metal alloy source contact layer located over a back side of the doped single crystalline semiconductor material layer, a dielectric isolation layer located over a front side of the doped single crystalline semiconductor material layer, an alternating stack of insulating layers and electrically conductive layers located over the dielectric isolation layer, a memory opening vertically extending through the alternating stack and the dielectric isolation layer and at least partially through the doped single crystalline semiconductor material layer, a memory film and a vertical semiconductor channel located within the memory opening, such that the vertical semiconductor channel vertically extends through the dielectric isolation layer and into the doped single crystalline semiconductor material layer, and a single crystalline semiconductor pedestal contacting the doped single crystalline semiconductor material layer and the vertical semiconductor channel.

Three-dimensional memory device containing epitaxial pedestals and top source contact

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of charge storage elements, a vertical semiconductor channel, a ferroelectric material layer located between the vertical stack of charge storage elements and the vertical semiconductor channel, and a blocking dielectric layer located between the ferroelectric material layer and the vertical semiconductor channel. A tunneling dielectric layer is located between at least one of the electrically conductive layers and the vertical stack of charge storage elements.

Three-dimensional memory device containing ferroelectric-assisted memory elements and method of making the same

A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening extending vertically through the alternating stack and including laterally-protruding portions at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a vertical stack of discrete ferroelectric memory structures located in the laterally-protruding portions of the memory opening. Each of the ferroelectric memory structures includes crystalline ferroelectric material portion and a crystalline template material portion located between a respective electrically conductive layer of the electrically conductive layers and the crystalline ferroelectric material portion.

Three-dimensional memory device containing templated crystalline ferroelectric memory elements and method of making thereof

A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a memory film. The memory film includes a contoured blocking dielectric layer including sac-shaped lateral protrusions located at levels of the electrically conductive layers, a tunneling dielectric layer in contact with the vertical semiconductor channel, and a vertical stack of charge storage material portions located within volumes enclosed by the sac-shaped lateral protrusions.

Three-dimensional memory device including discrete charge storage elements and methods of forming the same

A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a mask layer over the alternating stack, forming a cavity in the mask layer, forming a first cladding liner on a sidewall of the cavity in the mask layer, and forming a via opening the alternating stack by performing an anisotropic etch process that transfers a pattern of the cavity in the mask layer through the alternating stack using a combination of the first cladding liner and the mask layer as an etch mask.

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel, a memory film in contact with the vertical semiconductor channel, and a vertical stack of tubular dielectric spacers laterally surrounding the memory film. The tubular dielectric spacers may include tubular graded silicon oxynitride portions having a composition gradient such that an atomic concentration of nitrogen decreases with a lateral distance from an outer sidewall of the memory film, or may include tubular composite dielectric spacers including a respective tubular silicon oxide spacer and a respective tubular dielectric metal oxide spacer. Each of the electrically conductive layers has a hammerhead-shaped vertical cross-sectional profile.

Three-dimensional memory device including vertical stack of tubular graded silicon oxynitride portions

A method includes forming an alternating stack of first and second layers, forming a composite hard mask layer over the alternating stack, forming openings in the hard mask, and forming via openings through the alternating stack by performing an anisotropic etch process that transfers a pattern of the openings in the composite hard mask layer through the alternating stack. The compositing hard mask includes a first cladding material layer which has higher etch resistance than upper and lower patterning films of the composite hard mask.

A source-level semiconductor layer and an alternating stack of first material layers and second material layers is formed above a substrate. A hard mask layer is formed over the alternating stack, and is subsequently patterned to provide a pattern of cavities therethrough. Via openings are formed through the alternating stack by performing an anisotropic etch process. A cladding liner is formed on sidewalls of the cavities in the hard mask layer and on a top surface of the hard mask layer. The via openings are vertically extended at least through the source-level semiconductor layer by performing a second anisotropic etch process employing a combination of the cladding liner and the hard mask layer as an etch mask.

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Campbell, CA, United States of America

Raghuveer S Makala