International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Raghuveer Reddy Patlolla

Cornelius Brown Peethala

Chih-Chao Yang

Hari Prasad Amanapu

Benjamin David Briggs

Elbert Emin Huang

Takeshi Nogami

Donald Francis Canaperi

David Lee Rath

Theodorus E Standaert

Michael Rizzolo

Hosadurga K Shobha

Roger Allan Quon

James John Kelly

Charan V Surisetty

Joseph F Maniscalco

Prasad Bhosale

Hemanth Jagannathan

Christopher J Penny

Koichi Motoyama

Su Chen Fan

Brown Cornelius Peethala

Jassem Ahmed Abdallah

Alexander Reznicek

Son Van Nguyen

Soon-Cheon Seo

Baozhen Li

Oscar Van Der Straten

Hsueh-Chung Chen

Sanjay C Mehta

Xunyuan Zhang

Muthumanickam Sankarapandian

John Christopher Arnold

Wei Lin

Viraj Yashawant Sardesai

Vimal Kumar Kamineni

Dexin Kong

Spyridon Skordas

Troy Lawrence Graves-Abe

Iqbal Rashid Saraf

Mona Abdulkhaleg Ebrish

Kunaljeet Tanwar

Matthew T Shoudy

Mary Breton

Binglin Miao

Sugirtha Krishnamurthy

Pavan S Chinthamanipeta

A method of manufacturing a semiconducting device that includes forming first opening for forming bottom electrode hole in a first area of a semiconductor wafer; forming a deeper second opening for overlay/alignment hole in second area; depositing a bottom electrode metal layer filling the first opening to form a bottom electrode and partially filling the second opening. A layer of sacrificial material is then deposited above the bottom electrode layer and completely filling the second opening. A chemical-mechanical planarization process is performed to remove the -bottom electrode metal and -sacrificial layer, the -sacrificial material layer being removed above a surface defined atop the filled remaining portion above the second opening. The sacrificial layer material is removed in the remaining portion of the second opening. The second opening providing an overlay/alignment feature topography detectable for alignment by lithography and for overlay measurement on the overlay metrology tool.

Maskless alignment scheme for BEOL memory array manufacturing

A method for fabricating a planarized planarization layer for an integrated circuit device is described. A barrier layer is deposited over a planarization layer. Next, a liner layer is deposited on the barrier layer. An overburden layer is deposited on the liner layer. A first chemical mechanical polishing (CMP) process is performed on the overburden layer. A surface conversion process is performed on uncovered portions of a top surface of the planarization layer which are not protected by the polished overburden layer. A first wet etch is performed of the planarization layer. In embodiments, the first wet etch is selective to metal overburden layer as compared to the planarization layer. A second wet etch is performed removing the liner layer, the diffusion barrier layer and the metal overburden layer. In embodiments, the second wet etch is selective to the planarization layer as compared to the overburden layer.

Surface conversion in chemical mechanical polishing

A method including forming a dual damascene interconnect structure comprising a metal wire above a via, recessing the metal wire to form a trench, depositing a liner along a bottom and a sidewall of the trench, and forming a new metal wire in the trench. The method may also include forming a dual damascene interconnect structure comprising a metal wire above a via, recessing the metal wire to form a trench, depositing a liner along a bottom and a sidewall of the trench, removing the liner along the bottom of the trench, and forming a new metal wire in the trench.

Dual damascene with short liner

Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first dielectric layer from a first dielectric material. A first conductive interconnect is formed having a first conductive interconnect surface. The first conductive interconnect is positioned in a first portion of the first dielectric layer, and the first conductive interconnect surface has a first conductive interconnect surface area. A second conductive interconnect is formed having a second conductive interconnect surface. The second conductive interconnect is above the first conductive interconnect and positioned in a second portion of the first dielectric layer. The second conductive interconnect surface has a second conductive interconnect surface area that is less than a first conductive interconnect surface area of the first conductive interconnect. A planarization stop region is formed above the second conductive interconnect and in a third portion of the first dielectric layer.

Planarization stop region for use with low pattern density interconnects

Embodiments of the invention are directed to an interconnect stack including a first dielectric layer, a first trench formed in the first dielectric layer, and a first liner deposited in the first trench, wherein the first liner defines a second trench. A first conductive material is in the second trench and deposited over the first dielectric layer and the first conductive material. A third trench extends through the second dielectric layer and is over the first conductive material. A bottom surface of the third trench includes at least a portion of the top surface of the first conductive material. A second liner is in the third trench, on sidewalls of the third trench, and also on the portion of the top surface of the first conductive material. The second liner functions as a cap region configured to counter electro-migration or surface migration of the first conductive material.

Liner and cap structures for reducing local interconnect vertical resistance without compromising reliability

Interconnect structures or memory structures are provided in the BEOL in which topography variation is reduced. Reduced topography variation is achieved by providing a structure that includes a first dielectric capping layer that has a planar topmost surface and/or a second dielectric capping layer that has a planar topmost surface. The first dielectric capping layer has a non-planar bottom surface that contacts both a recessed surface of an interconnect dielectric material layer and a planar topmost surface of at least one electrically conductive structure that is embedded in the interconnect dielectric material layer.

Interconnect and memory structures having reduced topography variation formed in the BEOL

A semiconductor device structure includes an MRAM metallization stack. A via is disposed within a dielectric cap layer that is on and in contact with the metallization stack. A liner is disposed on sidewalls and a bottom surface of the via. A recessed electrode contact is disposed within a portion of the via and in contact with a first part of the liner in contact with sidewalls of the via. A second part of the liner is in contact with the sidewalls is above a top surface of the contact. A method for forming the semiconductor device structure includes forming a via within a MRAM metallization stack. The via exposes a top surface of the second metal layer. An electrode contact is formed within a portion of the via. A cap layer is formed within a remaining portion of the via in contact with a top surface of the electrode contact.

Controllable formation of recessed bottom electrode contact in a memory metallization stack

A method for implementing a wet clean process includes cleaning one or more trenches formed in an interlevel dielectric by applying a two-phase cleaning solution. Applying the two-phase cleaning solution includes applying a first component of the two-phase cleaning solution including a diluted acid solution, and reducing capillary force during drying by applying a second component of the two-phase cleaning solution including a chemistry that is less dense than the first component.

Wet clean solutions to prevent pattern collapse

Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.

Forming dual metallization interconnect structures in single metallization level

Techniques for planarization of dielectric topography that stop in dielectric are provided. In one aspect, a method for planarization includes: depositing a first dielectric onto a wafer having a surface topography with peaks and valleys; depositing a second, different dielectric onto the first dielectric; and polishing the second dielectric down to the first dielectric to form a planar surface at an interface between the first dielectric and the second dielectric. Optionally, a follow-up CMP or etch can be performed using a &#x2dc;1:1 selective polish or etch to completely remove the second dielectric and an equivalent amount of the first dielectric to form a planar surface devoid of the peaks and valleys in the first dielectric. A device structure formed by the present techniques is also provided.

Planarization of dielectric topography and stopping in dielectric

Interconnect structures and processes of fabricating the interconnect structures generally includes a recessed metal conductor and a discontinuous capping layer thereon. The discontinuous 'capped' metal interconnect structure provides improved performance and reliability for the semiconductor industry.

Metal interconnects

A semiconductor device and method of formation thereof. The semiconductor device includes a portion of a first material that abuts a portion of a second material and surrounds at least a portion of a semiconductor component. The first material has a first composition and a first index of refraction and is of a same type of material as the second material. The second material has a second composition and a second index of refraction. An opening in the first material exposes a portion of the semiconductor component.

Semiconductor structures of more uniform thickness

Embodiments of the invention describe a method of forming an integrated circuit. The method includes forming an active semiconductor device region over a substrate. A first contact structure is formed over the active semiconductor device region, wherein the first contact structure includes a first contact liner material and a first contact body material. A conductive gate structure is formed over the active semiconductor device region, and a first gate cap material is formed on the conductive gate structure. The first contact liner material includes a first etch selectivity responsive to a first etch composition, the first contact body material includes a second etch selectivity responsive to the first etch composition, and the first gate cap material includes a third etch selectivity responsive to the first etch composition. The first etch selectivity is greater than each of the second and third etch selectivies.

Robust gate cap for protecting a gate from downstream metallization etch operations

Growing community of inventors

Guilderland, NY, United States of America

Raghuveer Reddy Patlolla