Juniper Networks, Inc.

Raghuraman Thirumalairajan

Vijit V Nair

Sek Wing Siu

Sunil Mekad

Eswaran Srinivasan

Alam Yadav

Manjunath Mandigatta Navilappa

Karthikeyan Veerabadran

Dhairyashil Patil

Balaji Mohan

A network device may include a packet generator device implemented in hardware. The packet generator device may include a control component, a payload generation component, and an interface element to receive test packet generation information. The test packet generation information may include one or more control inputs, header data that is to be included in one or more test packets, and information regarding a data pattern that is to be included in payload data of the one or more test packets. The one or more control inputs, when provided to the control component, may cause the control component to control the payload generation component to generate the one or more test packets based on the header data and the information regarding the data pattern.

Built-in test traffic generator

A system may include a set of 4N packet processors and a switching fabric to interconnect the set of 4N packet processors. The switching fabric may include the following switching elements having a size of at least 3N&#xd7;3N: a first switching element, a second switching element, a third switching element, and a fourth switching element. The first switching element may be directly connected to the second switching element and the third switching element, and may be indirectly connected to the fourth switching element. The second switching element may be directly connected to the fourth switching element, and may be indirectly connected to the third switching element. The third switching element may be directly connected to the fourth switching element.

Switching fabric topology based on traversing asymmetric routes

A switch interface board may include a first serializer/deserializer to communicate with a first group of packet processing components of a first chassis via a first port. The first chassis may house the switch interface board and the first group of packet processing components. The switch interface board may include a second serializer/deserializer to communicate with a second switch interface board of the first chassis via a second port. The second switch interface board may be connected to a second group of packet processing components of the first chassis. The second group of packet processing components may be different from the first group of packet processing components. The switch interface board may include a third port to communicate with a third switch interface board of a second chassis or a switching device of a cross-connect chassis.

Multi-mode switch interface board

Growing community of inventors

Pleasanton, CA, United States of America

Raghuraman Thirumalairajan