Analog Bits Inc.

Sun Microsystems, Inc.

Other

Raghunand Bhagwan

Alan C Rogers

Kowshik Murali

John F MacDonald

A quick release and connect system that provides battery power for a wearable electronic device and a method for reducing battery charging down time of a wearable electronic device are disclosed. The quick release and connect system that provides battery power for a wearable electronic device and the method for reducing battery charging down time of a wearable electronic device reduces battery charging down time of a wearable electronic device by swapping of attachable-detachable auxiliary components with auxiliary batteries.

Quick battery recharge system for wearable electronic devices

Quick release and connect system that provides battery power for a wearable electronic device and method for reducing battery charging down time of a wearable electronic device

Implementations provide a phase locked loop (PLL) device that includes: a phase and frequency detector (PFD) and charge pump (CP) portion; a low pass filter; a voltage controlled oscillator (VCO) driven by the low pass filter to generate a VCO clock signal, multiple divider configured to receive the VCO clock signal and frequency divide the VCO clock signal in stages to generate a series statically divided VCO clock signals and a dynamically divided VCO clock signal; a feedback portion including a first component configured to receive the dynamically divided VCO clock signal and generate indicator signals; and a second component configured to multiplex from the indicator signals to generate the feedback clock signal set for the PFD and CP portion; and a master phase/frequency control engine configured to assert a division control over at least one divider and a multiplex control over the multiplex network.

Method and circuits for fine-controlled phase/frequency offsets in phase-locked loops

A charge pump includes: (I) a current source; (II) a p-channel source current network including: a first p-channel transistor; a second p-channel transistor; a p-channel current switch including at least one source terminal coupled to the drain terminal of the first p-channel transistor, at least one gate coupled to a phase comparator, and at least one drain terminal; a third p-channel transistor; and (III) a n-channel sink current network including: a first n-channel transistor; a second n-channel transistor; a third n-channel transistor; a n-channel current switch comprising at least one drain terminal coupled to the source terminal of the third n-channel transistor, at least one gate coupled to the phase comparator; and at least one source terminal coupled to the drain terminal of the first n-channel transistor; and wherein the p-channel source current network and the n-channel sink current network draw a baseline current from the first p-channel transistor.

Method and circuits for charge pump devices of phase-locked loops

A phase locked loop (PLL) includes: a phase frequency detector configured to: generate one or more comparison signals indicating whether a reference input signal is leading a feedback signal or whether the feedback signal is leading the reference input signal; a charge pump coupled to the phase frequency detector and configured to convert the one or more comparison signals into a driving current; a loop filter coupled to the charge pump and configured to split the driving current to generate a first voltage signal and a second voltage signal; and a voltage controlled oscillator coupled to the loop filter and configured to: receive the first voltage signal and generate a first control current; receive the second voltage signal and generate a second control current; and combine the first and second control currents to jointly drive a charge controlled oscillator such that the output signal of a desired frequency is generated.

Method and circuits for reducing noise in phase-locked loops

A phase lock loop (PLL) includes: a binary phase detector configured to generate a first and second polarity signals that respectively indicating whether an incoming data stream is leading a feedback signal, or whether the feedback signal is leading the incoming data stream, wherein a difference between the first and second polarity signals does not represent an amount of phase difference between the incoming data stream and the feedback signal; a digital filter configured to: generate filtered first polarity signal on a first path and a second path that are different; and generate filtered second polarity signal on a third path and a fourth path that are different; a charge pump coupled to the digital filter and configured to: integrate the filtered first polarity signal and the filtered second polarity signal; and an oscillator configured to generate the synthesized clock signal serving as the feedback signal.

Method and circuits for phase-locked loops

A voltage controlled current source provides controlled current to a current controlled oscillator in a high frequency phase-locked loop clock generator. The voltage controlled current source receives a first control signal and a set of second control signals indicative of a phase difference between the output signal of the clock signal generator and a reference frequency. It uses those control signals to adjust the current-controlled oscillator. A level shifter coupled to the current-controlled oscillator amplifies the oscillator signals to full rail and adjusts the duty cycle at its output to 50% to produce the clock signal generator output signal.

Current-regulated, voltage-controlled oscillator with duty cycle

A phased lock loop (PLL) clock circuit generates a clock signal at 1x the desired clock frequency while maintaining substantially a 50% duty cycle. A first loop provides a feedback signal to maintain clock frequency, while a second loop provides a feedback signal and controls duty cycle. Two clock signals from a ring oscillator are fed to a level shifter, where each clock signal triggers a respective rising or trailing edge of the output clock signal. The level shifter is provided with a delay for controlling timing of the trailing edge of the output clock signal. The output clock signal is fed to a equi-current buffer where a charge pump, driven by the output clock signal, charges and discharges a capacitor in proportion to the duty cycle of the output clock signal, producing a feedback control voltage. The feedback control voltage is applied to the delay of the level shifter to maintain a substantially 50% duty cycle. The clock circuit of the present invention has improved power supply noise immunity and control voltage headroom for operation at different design frequencies.

Dual loop PLL with secondary loop to achieve 50% duty cycle

An oscillator runaway detection circuit is provided with a synchronous delay line such that energy saving or sleep modes of operation are not mischaracterized as oscillator runaway. A Schmitt trigger monitors oscillator control voltage at a filter capacitor. If the control voltage is below a predetermined limit, indicating a possible runaway condition, a signal is output to a synchronous delay line. The output of the Schmitt trigger is propagated through the synchronous delay line comprising a plurality of flip-flops clocked by the system reference clock. The output of the synchronous delay line drives a transistor which in turn may charge the filter capacitor to reduce the control voltage and thus lower the frequency of the oscillator. A one-shot coupled to the clock tree monitors for clock activity in the clock tree. If clock activity is present, it is presumed that a runaway condition does not exist, and the output of the one-shot resets the flip-flops in the delay line, preventing the output of the Schmitt trigger to charge/reset the oscillator.

Oscillator runaway detect and reset circuit for PLL clock generator

An apparatus and method for instantaneously stretching multi-phase clock signals includes a delay line to generate a plurality of multi-phase clock signals. An instantaneous signal stretch logic circuit is connected to the delay line. The instantaneous signal stretch logic circuit transforms the plurality of multi-phase clock signals into stretched multi-phase clock signals in response to a filter capacitor analog signal and a digital stretch signal. Multiple embodiments of the instantaneous signal stretch logic circuit are disclosed. However, each embodiment includes dual current control paths with a single current control path responsive to the digital stretch signal, which is preferably a single bit value.

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Sunnyvale, CA, United States of America

Raghunand Bhagwan