Micron Technology Incorporated

Raghukiran Sreeramaneni

Jennifer E Taylor

Sujeet V Ayyapureddi

Daniel B Penney

William J Wilcox

Girish N Cherussery

Suryanarayana B Tatapudi

Hideyuki Ichida

Liang Liu

John E Riley

Yu-Feng Chen

Ramachandra R Jogu

A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.

Memory decision feedback equalizer

An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.

Apparatuses and methods for compensating for crosstalk noise at input receiver circuits

Embodiments of the disclosure are drawn to apparatuses, systems, and methods for analog row access rate determination. Accesses to different row addresses may be tracked by storing one or more received addresses in a slice of stack. Each slice includes an accumulator circuit which provides a voltage based on charge on a capacitor. When a row address is received, it may be compared to the row addresses stored in the stack, and if there is a match, the charge on the capacitor in the associated accumulator circuit is increased. Each slice may also include a voltage to time (VtoT) circuit which may be used to identify the highest of the voltages provided by the accumulator circuits. The row address stored in the slide with the highest voltage may be refreshed.

Apparatuses, systems, and methods for analog accumulator for determining row access rate and target row address used for refresh operation

A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.

Decision feedback equalizer

Apparatus and method including analog accumulator for determining row access rate and target row address used for refresh operation

A device includes a fuse-array mat including a plurality of fuse-array elements. Each fuse-array element includes a fuse comprising a fuse line having less than or equal to 50% of a dimension of the fuse line disposed over an active area of the fuse-array element, wherein the fuse is configured to be activated to indicate a fuse state of the fuse of two possible fuse states of the fuse. Additionally, each fuse-array element includes an access device comprising a gate line having more than 50% of a dimension of the gate line disposed over the active area of the fuse-array element.

Fuse-array element

A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference signal and generate a plurality of bias level signals based at least in part on the reference signal. The multi-level bias generator transmits the plurality of bias level signals to a plurality of multiplexers that each receive a select signal to select a subset of bias level signals of the plurality of bias level signals. The device also includes an adjustment circuit of a decision feedback equalizer that receives a respective selected subset of bias level signals from one multiplexer of the plurality of multiplexers and utilizes the respective selected subset of bias level signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.

Analog multiplexing scheme for decision feedback equalizers

A device includes a signal input to receive a data input as part of a bit stream. The device also includes a reference input to receive a reference signal. The device further includes push circuitry to receive a first weight value, receive a first correction value, and generate a push signal based on the first weight value and the first correction value to selectively modify the data input as well as pull circuitry to receive a second weight value, receive a second correction value, and generate a pull signal based on the second weight value and the second correction value to selectively modify the data input.

Voltage reference computations for memory decision feedback equalizers

A device includes a selection circuit that is configured to generate a bias level. The device also includes a combinational circuit coupled to the selection circuit. The combinational circuit is configured to generate a distortion correction factor used offset inter-symbol interference from a data stream on a distorted bit based on the bias level to generate a correction signal. The device additionally includes a latching element coupled to the combinational circuit and configured to receive the first correction signal.

Memory decision feedback equalizer bias level generation

A method of operating an electronic device includes: precharging a fuse read node to an intermediate voltage less than an input voltage, wherein the fuse read node connects a fuse array and a fuse read circuit, the fuse array including a fuse cell configured to store information and the fuse read circuit configured to read the stored information; connecting the fuse cell to the fuse read node for reading the information; and determining, with the fuse read circuit, the information from the fuse cell based on changes to the intermediate voltage at the fuse read node.

Electronic device with a fuse read mechanism

A device includes one or more memory banks configured to store data. The device also includes a data receiver configured to receive distorted input data as part of a data stream, apply a correction factor to the distorted input data to offset inter-symbol interference from the data stream on the distorted input data, and generate the data by applying the correction factor to the distorted data. The device further includes a test circuit internal to the device, wherein the test circuit is configured to generate the data stream.

Growing community of inventors

Frisco, TX, United States of America

Raghukiran Sreeramaneni