Intel Corporation

Altera Corporation

Raghucharan Boddupalli

Debendra Das Sharma

Swadesh Choudhary

Michelle C Jen

Sreedhar Ravipalli

Luan Bui

Ranjini Rajeevan

Jing Miao

Dinesh Kotti

Systems or methods of the present disclosure may include a programmable logic device having a first portion of programmable elements configured to implement a user logic. The programmable logic device also includes a second portion of the programmable elements. The second portion is configured to implement an infrastructure processing unit (IPU) to enable the first portion of programmable elements to interface with a plurality of accelerator engines. The IPU is to receive a chained command to cause two or more accelerator engines of the plurality of accelerator engines to perform sequential operations on a data packet in response to the chained command.

Chained command architecture for packet processing

A device includes a port with a replay buffer and protocol logic to receive a flit in a sequence of flits to be sent on a point-to-point link and determine an error in the flit. Based on the error, a copy of the flit is stored in a first position within the replay buffer as well as a copy of a next flit received in the sequence of flits, which is stored in a second position within the replay buffer. The copies of the flits are then written to a register for access by software.

Hardware logging for lane margining and characterization

Growing community of inventors

Bengaluru, India

Raghucharan Boddupalli