Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Raghu Voleti

Nitin Kumar Gupta

Bhavin Odedara

Srikanth Bojja

Systems and methods for power distribution are disclosed. A system includes a first power domain that supplies current to an integrated circuit at a first voltage level, a second power domain that supplies current to the integrated circuit at a second voltage level, and a current distribution component that is connected to the first power domain and connectable to the second power domain and senses a metric comprising a first current level or a first voltage level drawn from the first power domain, determines whether the metric exceeds a first threshold, and in response to determining that the metric exceeds the first threshold, electrically connects the second power domain to the integrated circuit to supply additional current such that an aggregate current level received by the integrated circuit comprises current from the first power domain and the additional current from the second power domain.

Current distribution from different power sources

A clock generation circuit includes a delay chain configured to generate an N-number of clock signals at a frequency multiple that is M-times the frequency of a reference clock signal. To generate the clock signals at the frequency multiple, a multiplexer selectively inputs, to the delay chain, a delayed reference clock signal and a last clock signal generated by a last delay cell of the delay chain. In addition, a delay control generator circuit periodically compares the phases of the delayed reference clock signal and the last clock signal to set the delay of the delay chain. The clock generation circuit generates the N-number of clock signals at the frequency multiple in response to receipt of the reference clock signal, and continues to generate the clock signals at the frequency multiple when the reference clock signal is no longer being received.

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San Jose, CA, United States of America

Raghu Voleti