Qualcomm Incorporated

Raghu Sankuratri

Subbarao Palacharla

Alain Artieri

Vinod Chamarty

Michael Drop

Jian Mao

Kedar Bhole

Moinul H Khan

Marzio Pedrali-Noy

Xuhao Huang

Deepti Vijayalakshmi Sriramagiri

Nicholas K Yu

Edwin Jose

Laurent Rene Moll

Yanru Li

Sanjay K Jha

George Patsilaras

Andrew Edmund Turner

Kenneth David Easton

Albert Scott Ludwin

Richard Higgins

Mehraban Iraninejad

Safi Khan

Pankaj Chaurasia

Jeong-Ho Woo

Chauhung Lee

Pavan Kumar Thirunagari

Deepti Sriramagiri

Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

Method and apparatus for a shared cache with dynamic partitioning

A cache controller adaptively partitions a shared cache. The adaptive partitioning cache controller includes tag comparison and staling logic and selection logic that are responsive to client access requests and various parameters. A component cache is assigned a target occupancy which is compared to a current occupancy. A conditional identification of stale cache lines is used to manage data stored in the shared cache. When a conflict or cache miss is identified, selection logic identifies candidates for replacement preferably among cache lines identified as stale. Each cache line is assigned to a bucket with a fixed number of buckets per component cache. Allocated cache lines are assigned to a bucket as a function of the target occupancy. After a select number of buckets are filled, subsequent allocations result in the oldest cache lines being marked stale. Cache lines are deemed stale when their respective component cache active indicator is de-asserted.

System and method for a shared cache with adaptive partitioning

Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.

Method and apparatus for flexible cache partitioning by sets and ways into component caches

A method for data synchronization is provided according to certain embodiments. The method comprises receiving data, a data clock signal, and a clean clock signal, sampling the data using the data clock signal, synchronizing the sampled data with the clean clock signal, and outputting the synchronized sampled data. The method also comprises tracking a phase drift between the data clock signal and the clean clock signal, and pulling in the output of the synchronized sampled data by one clock cycle of the clean clock signal if the tracked phase drift reaches a first value in a first direction.

Low latency synchronization scheme for mesochronous DDR system

In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals.

Dual channel memory architecture having reduced interface pin requirements using a double data rate scheme for the address/control signals

A memory structure is described. In one embodiment, the memory structure comprises a memory controller configured to receive a clock signal and to be coupled to a plurality of memory modules via a single address/control bus. The memory controller couples to each of the plurality of memory modules via a separate chip select signal for each memory module. The memory controller issues commands across the address/control bus to the memory modules in an interleaved fashion in accordance with the timing supplied by the clock. During a waiting period after issuance of a command to one memory module, the memory controller can issue commands to a different memory module.

Hybrid single and dual channel DDR interface scheme by interleaving address/control signals during dual channel operation

Dual channel memory architecture having a reduced interface pin requirements using a double data rate scheme for the address/control signals

The dual microprocessor system includes one microprocessor configured to perform wireless telephony functions and another configured to perform personal digital assistant (PDA) functions and other non-telephony functions. A memory system and a digital signal processor (DSP) are shared by the microprocessors. By providing a shared memory system, data required by both data microprocessors is conveniently available to both of the microprocessors and their peripheral components thereby eliminating the need to provide separate memory subsystems and further eliminating the need to transfer data back and forth between the separate memory subsystems. By providing a shared DSP, separate DSP devices need not be provided, yet both microprocessors can take advantage of the processing power of the DSP. In a specific example described herein, the microprocessors selectively program the DSP to perform, for example, vocoder functions, voice recognition functions, handwriting recognition functions, and the like.

Mobile communication device having dual micro processor architecture with shared digital signal processor and shared memory

A technique for activating an active-mode high frequency clock following a sleep period for use within a mobile station wherein selected components of the mobile station operate using a low power, low frequency sleep-mode clock during the sleep period and the faster high frequency active-mode clock during non-sleep periods. In one embodiment, the technique is implemented by a device having a wake-up estimation unit for estimating a wake up time using the sleep-mode clock and a frequency drift compensation unit for compensating for any error in the estimated wake up time caused by frequency drift in the sleep-mode clock. An off-set time compensation unit is also provided for compensating for a lack of precision in the low frequency sleep-mode clock resulting in a possible error in the estimated wake up time. The lack of precision can result in an initial timing off-set error at the beginning of the sleep period and an final timing off-set error at the end of the sleep period. Both the frequency drift compensation unit and the off-set time compensation unit employ a high frequency transition-mode clock signal for use in calculating the time required to adjust the wake-up time. The transition-mode clock, which may have the same frequency as the active-mode clock, is employed only at the beginning and end of the sleep period and is deactivated throughout most of the sleep period to reduce power consumption.

Method and apparatus for activating a high frequency clock following a sleep mode within a mobile station operating in a slotted paging mode

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San Diego, CA, United States of America

Raghu Sankuratri