Intel Corporation

Marvell International Limited

Marvellworld Trade Ltd.

Axiado Corporation

Raghu R Kondapalli

Alexander Bachmutsky

Francesc Guim Bernat

Kshitij Arun Doshi

Ned M Smith

Suraj Prabhakaran

Donald Robert Pannell

Vadim Sukhomlinov

Guy Hutchison

Trevor Cooper

John Bergen

Antonino Albarran

Jaime Sanz

Gopi Sirineni

Vedvyas Shanbhogue

Tsung-Yuan Charles Tai

Ren Wang

Andrew J Herdrich

Yipeng Wang

Doddaballapur N Jayasimha

Yifan Yuan

Arasch Lagies

Alex Lin

Guy T Hutchison

Provided herein are method and systems for detecting a side-channel attack on a target in a network, comprising conducting a training operation comprising collecting measurements of a physical parameter of a target over a period of time and conducting a detection operation comprising monitoring the physical parameter of the target.

Machine learning methods and systems for detecting platform side-channel attacks

Described are methods, systems, and media for detecting malicious activity in a network by performing operations comprising: feeding network packets from the network into a header crypto engine; sending the network packets from the header crypto engine to a work scheduler; divaricating the network packets using the work scheduler based on flow data and header data of the network packets to at least one of a firewall and a neural network processor; generating output data comprising: a first output data from the firewall according to rules of the firewall; a second output data from the neural network processor based on behavioral analysis performed by the neural network processor, wherein the second output data is used to update the rules in the firewall; and aggregating the output data from the firewall and the neural network processor to detect malicious activity in the network.

Systems and methods using network artificial intelligence to manage control plane security in real-time

Technologies for collecting metrics associated with a processing resource (e.g., central processing unit (CPU) resources, accelerator device resources, and the like) over a time window are disclosed. According to an embodiment presented herein, a network device receives, in an edge network, a request to provide one or more metrics associated with a processing resource, the request specifying a window indicative of a time period to capture the one or more metrics. The network device obtains the one or more metrics from the processing resource for the specified window and provides the obtained one or more metrics in response to the request.

Technologies for capturing processing resource metrics as a function of time

Technologies for providing a multi-tenant local breakout switching and dynamic load balancing include a network device to receive network traffic that includes a packet associated with a tenant. Upon a determination that the packet is encrypted, a secret key associated with the tenant is retrieved. The network device decrypts a payload from the packet using the secret key. The payload is indicative of one or more characteristics associated with network traffic. The network device evaluates the characteristics and determines whether the network traffic is associated with a workload requesting compute from a service hosted by a network platform. If so, the network device forwards the network traffic to the service.

Technologies for multi-tenant automatic local breakout switching and data plane dynamic load balancing

Technologies for dynamic allocation of network communication resources includes a resource manager server to allocate a set of network communication resources to a compute device through an expansion bus switch that is coupled to the compute device and to the network communication resources. The resource manager server obtains telemetry data indicative of a present utilization of the allocated set of network communication resources and determines whether the present utilization satisfies a predefined utilization threshold. Additionally, the resource manager server adjusts, through the expansion bus switch and in response to a determination that the present utilization does not satisfy the predefined utilization threshold, an amount of network communication resources in the set to the compute device.

Technologies for flexible and automatic mapping of disaggregated network communication resources

Examples described herein relate to requesting execution of a workload by a next function with data transport overhead tailored based on memory sharing capability with the next function. In some examples, data transport overhead is one or more of: sending a memory address pointer, virtual memory address pointer or sending data to the next function. In some examples, the memory sharing capability with the next function is based on one or more of: whether the next function shares an enclave with a sender function, the next function shares physical memory domain with a sender function, or the next function shares virtual memory domain with a sender function. In some examples, selection of the next function from among multiple instances of the next function based on one or more of: sharing of memory domain, throughput performance, latency, cost, load balancing, or service legal agreement (SLA) requirements.

Scalable and accelerated function as a service calling architecture

Various systems and methods for implementing a service-level agreement (SLA) apparatus receive a request from a requester via a network interface of the gateway, the request comprising an inference model identifier that identifies a handler of the request, and a response time indicator. The response time indicator relates to a time within which the request is to be handled indicates an undefined time within which the request is to be handled. The apparatus determines a network location of a handler that is a platform or an inference model to handle the request consistent with the response time indicator, and routes the request to the handler at the network location.

Service level agreement-based multi-hardware accelerated inference

A central processing unit can offload table lookup or tree traversal to an offload engine. The offload engine can provide hardware accelerated operations such as instruction queueing, bit masking, hashing functions, data comparisons, a results queue, and a progress tracking. The offload engine can be associated with a last level cache. In the case of a hash table lookup, the offload engine can apply a hashing function to a key to generate a signature, apply a comparator to compare signatures against the generated signature, retrieve a key associated with the signature, and apply the comparator to compare the key against the retrieved key. Accordingly, a data pointer associated with the key can be provided in the result queue. Acceleration of operations in tree traversal and tuple search can also occur.

Offload of data lookup operations

Examples are described that relate to waking up or invoking a function such as a processor-executed application or a hardware device. The application or a hardware device can specify which sources can cause wake-ups and which sources are not to cause wake-ups. A device or processor-executed software can monitor reads from or writes to a region of memory and cause the application or a hardware device to wake-up unless the wake-up is specified as inhibited. The updated region of memory can be precisely specified to allow a pinpoint retrieval of updated content instead of scanning a memory range for changes. In some cases, a write to a region of memory can include various parameters that are to be used by the woken-up application or a hardware device. Parameters can include a source of a wake-up, a timer to cap execution time, or any other information.

Wake-up and timer for scheduling of functions with context hints

Technologies for providing hardware resources as a service with direct resource addressability are disclosed. According to one embodiment of the present disclosure, a device receives a request to access a destination accelerator device in an edge network, the request specifying a destination address assigned to the destination accelerator device. The device determines, as a function of the destination address, a location of the destination accelerator device and sends the request to the destination accelerator device.

Technologies for providing hardware resources as a service with direct resource addressability

A processor comprises a core, a cache, and a ZCM manager in communication with the core and the cache. In response to an access request from a first software component, wherein the access request involves a memory address within a cache line, the ZCM manager is to (a) compare an OTAG associated with the memory address against a first ITAG for the first software component, (b) if the OTAG matches the first ITAG, complete the access request, and (c) if the OTAG does not match the first ITAG, abort the access request. Also, in response to a send request from the first software component, the ZCM manager is to change the OTAG associated with the memory address to match a second ITAG for a second software component. Other embodiments are described and claimed.

Technology for moving data between virtual machines without copies

An apparatus for training artificial intelligence (AI) models is presented. In embodiments, the apparatus may include an input interface to receive in real time model training data from one or more sources to train one or more artificial neural networks (ANNs) associated with the one or more sources, each of the one or more sources associated with at least one of the ANNs; a load distributor coupled to the input interface to distribute in real time the model training data for the one or more ANNs to one or more AI appliances; and a resource manager coupled to the load distributor to dynamically assign one or more computing resources on ones of the AI appliances to each of the ANNs in view of amounts of the training data received in real time from the one or more sources for their associated ANNs.

Growing community of inventors

San Jose, CA, United States of America

Raghu R Kondapalli