Cadence Design Systems, Inc.

Facebook, Inc.

Mentor Graphics Corporation

Raghu Prasad Chalasani

Steven L Teig

Akira Fujimura

Lei Huang

Nicolas Bailey Cobb

Renbin Peng

Ziheng Wang

Jianyu Wang

Guangshuo Liu

Sergiy Komirenko

Systems, methods, and non-transitory computer-readable media can receive a set of video frames associated with a video. A determination can be made that a threshold number of video frames of the set of video frames depict two or more reaction icons of a set of reaction icons. The video can be identified as a poll video based on the determining that the threshold number of video frames of the set of video frames depict two or more reaction icons of the set of reaction icons.

Systems and methods for automated video classification

The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network.

Method and system for distributing clock signals on non manhattan semiconductor integrated circuits

Aspects of the invention relate to techniques for compensating flare effects in a lithographic process for an array of identical circuits to be fabricated on a wafer. According to various implementations of the invention, a reference circuit is selected from the array of identical circuits and intolerable flare difference regions are determined based on flare difference layers and tolerable flare difference layers. The lithographic process result for the array of identical circuit may be derived from that for the reference circuit and the intolerable flare difference regions.

Tolerable flare difference determination

Method and system for distributing clock signals on non Manhattan semiconductor integrated circuits

Method and system for distributing clock signals on non manhattan semiconductor integrated circuit using parameterized rotation

Method and system for distributing clock signals on non-Manhattan semiconductor integrated circuits

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San Jose, CA, United States of America

Raghu Prasad Chalasani