Texas Instruments Corporation

Raghavendra Santhanagopal

Rejitha Nair

Kazunobu Shin

Siva Srinivas Kothamasu

Chunhua Hu

Venkateswar Reddy Kowkutla

John Chrysostom Apostol

Jason Lynn Peck

Anthony Frederick Seely

Nishanth Menon

Rajesh Kumar Vanga

Charles Gerlach

Varun Singh

Venkateswara Reddy Pothireddy

Ravi Teja Reddy

Rajagopal Kollengode Ananthanarayanan

A circuit device is provided and includes a first power domain comprising a universal serial bus (USB) subsystem and/or a memory controller subsystem. The first power domain is configured to isolate the USB subsystem and/or the memory controller subsystem from a power-on-reset signal asserted during a low power mode.

Power-on-reset signal isolation during lower power mode

A system, e.g., a system on a chip (SoC) includes a first domain including a first processor configured to boot the system; a second domain including a processing subsystem having a second processor; and isolation circuitry between the first domain and the second domain During boot-up of the system, the first processor provides code to the second domain. When the code is executed by the second processor, it configures the processing subsystem as either a safety domain or as a general-purpose processing domain. The safety domain may an external safety domain or an internal safety domain.

System on a chip with an integrated configurable safety master microcontroller unit

In described examples, an integrated circuit (IC) includes an isolation, an input/output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.

Integrated circuit with low power mode management

A system on a chip (SoC) includes a first domain comprising a first processor configured to boot the SoC, and a first debug subsystem, a second domain comprising a second processor, the second domain configurable as either a safety domain or a general-purpose processing domain, and isolation circuitry between the first domain and the second domain. During boot-up of the SoC, the first processor provides code to the second domain which, when executed by the second processor, configures the second domain as either a safety domain or as a general-purpose processing domain.

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Dallas, TX, United States of America

Raghavendra Santhanagopal