Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Raghavendra Gopalakrishnan

Kalpit Bordia

Dmitry Vaysman

Joanna Lai

Ramanathan Muthiah

Karin Inbar

Ramkumar Ramamurthy

Vinayak Bhat

Ritesh Tiwari

Vinay Vijendra Kumar Lakshmi

Vivek Kumar

Bhanushankar Doni

Nicholas Thomas

Pradeep Sreedhar

Bhanushankar Doni Gurudath

Raviraj R

Manohar Srinivasaiah

Sachin Krishna Kudva

Ashim Ranjan Saikia

Prashanth Reddy Enukonda

Pankaj Dixit

A storage device maintains uniform write performance for data written to a memory device including varying block sizes. The storage device includes a balancing module to ensure that free blocks exist in a partition on the memory device and to define a garbage collection threshold based on blocks available in the partition. The storage device also includes a controller to receive host data from a host device, write the host data to the memory device; and relocate the host data in the memory device during a background operation. The controller initiates the background operation on the memory device at the garbage collection threshold and executes the background operation according to a host write-to-relocation write ratio based on a dynamically calculated size of the remaining free blocks in the partition.

Free space management in storage devices having non-uniform-sized memory blocks

Aspects are provided for optimizing game loading and rendering using an RMB dedicated for predicted host data that is accessible to a host and to a controller of a storage device. The controller obtains a bitmap indicating a status of a buffer in the RMB, receives from the host a read command indicating a logical address, predicts and reads from an NVM host data associated with a predicted logical address that is subsequent to the logical address, and loads the host data in the buffer in the RMB if the buffer is free. Subsequent read commands indicating the predicted logical address may lack PRP addresses in response to the host data being loaded in the RMB, while completion queue elements in response to such commands may include PRP addresses in the RMB where the host data is stored. Thus, command creation and completion overhead may be reduced using the RMB.

Optimized SSD for game loading and rendering

Aspects of a storage device provide an optimized data relocation scanning process which significantly reduces a number of page reads performed during a block relocation scan by consolidating logical addresses for multiple FMUs in a single FMU. The storage device includes a memory comprising a block including pages and FMUs, and a controller that is configured to store, in one of the FMUs, logical addresses for multiple FMUs. The controller is further configured, in response to a data relocation command, to read the logical addresses from the FMU, to determine at least one of the read logical addresses is mapped to a current FMU in a L2P mapping table, and to relocate data stored at the valid logical addresses in response to the determination. As a result, latency and power consumption associated with data relocation may be significantly reduced and storage device performance may thus be improved.

Smart relocation scan optimization

Aspects of the disclosure are directed to a storage device including a memory and a controller. The memory may include a plurality of flash memory blocks such as single level cell (SLC) blocks and multi-level cell (MLC) blocks. The controller may maintain a read count of each of the SLC blocks to determine which of the blocks contains data associated with the highest number of read commands. Based on the read commands, the controller may relocate the associated data into pages of MLC blocks that have a lower number of senses required to read the data stored in those blocks.

Encoding-aware data routing

The present disclosure generally relates to using irregular MetaBlocks (IRMBs) in both host and control pools. The IRMBs are used to ensure efficient wear leveling. Blocks in the control pool are swapped with blocks in the host pool upon exceeding a program-erase count (PEC) threshold. Additionally, the swapping algorithm for IRMBs can be used to ensure an efficient recovery from an ungraceful shutdown (UGSD) event.

Method of handling irregular MetaBlock wear leveling and UGSD boot time improvement

A storage device having a wide range of operating temperatures is disclosed. Techniques disclosed herein may be used to operate MLC cells at higher temperatures before resorting to thermal throttling. Techniques disclosed herein may be used to operate MLC cells at lower temperatures without needing to pre-heat the storage device. SLC data stored in a first group of memory cells is folded to MLC data stored in a second group of memory cells while an operating temperature is outside a first temperature range. After the operating temperature is within a second temperature range, the data integrity of the MLC data is checked. The SLC data in the first group is folded to MLC data in a third group of memory cells responsive to the MLC data in the second group failing the data integrity check. The foregoing permits the storage device to increase its range in operating temperatures.

Extending operating temperature of storage device

An apparatus comprising non-volatile memory is configured to access a selected unit of encoded SLC data in the non-volatile memory during a first programming phase of a process of folding data stored at a single bit per memory cell to data stored at multiple bits per memory cell. The apparatus recovers the selected unit of SLC data based on redundancy data formed from units of SLC data that data include the selected unit of SLC data. The apparatus saves the recovered selected unit of SLC data to memory. The apparatus uses the saved recovered unit of SLC data during a second programming phase of folding the data stored at a single bit per memory cell to the data stored at multiple bits per memory cell, thereby saving considerable time in not having to again recover the SLC data using the redundancy data.

Uncorrectable error correction code (UECC) recovery time improvement

A storage system and method are disclosed for generating a reverse map during a background operation and storing it in a host memory buffer. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to generate a physical-to-logical address map for at least part of the memory as a background operation and send the physical-to-logical address map to a host for storage in volatile memory in the host.

Storage system and method for generating a reverse map during a background operation and storing it in a host memory buffer

In one embodiment, there is a method for managing data in a storage device comprising a non-volatile memory having a plurality of jumbo blocks, each jumbo block having a separate and distinct physical block address. The method comprises performing a folding operation data associated with a first virtual address from a plurality of Single Level Cell (SLC) jumbo blocks of the non-volatile memory to one Multilevel Cell (MLC) jumbo block of the non-volatile memory, receiving a read request to read data associated with a first logical block address, identifying that the first virtual address is associated with the first logical block address, determining whether a jumbo block associated with the first logical block address meets pre-SLC-overwrite criteria. In response to a determination that the jumbo block associated with the first logical block address meets pre-SLC-overwrite criteria, reading data from the SLC jumbo block associated with the first virtual address. In response to a determination that the jumbo block associated with the first logical block address does not meet pre-SLC-overwrite criteria, reading data from the MLC jumbo block associated with the first virtual address.

Smart mapping table update post background operations

Apparatus, systems, methods, and computer program products for buffering storage device data in a host memory buffer (HMB) are presented. A non-volatile memory and a controller are in communication with a non-volatile memory. A controller is configured to receive an input/output (I/O) operation including data. A controller is configured to transmit at least a portion of data to an HMB of a host device separate from a non-volatile memory and a controller for storage until a trigger event occurs.

Buffering storage device data in a host memory buffer

Apparatuses, systems, and methods are disclosed for error characterization for control of non-volatile memory. An apparatus may include an array of non-volatile memory cells and a controller. A controller may be configured to acquire an error characterization for a region of memory. Also, an error characterization may comprise information about one or more types of errors to which a region of memory is susceptible. A controller may be configured to assign a region of memory into a logical group based on an error characterization. Further, a logical group may comprise a plurality of regions of memory. Additionally, a controller may be configured to service a write request by striping data across multiple regions assigned to a logical group.

Error characterization for control of non-volatile memory

An example of a system includes a host interface, a set of non-volatile memory cells, and one or more control circuits coupled to the host interface and coupled to the set of non-volatile memory cells. The one or more control circuits include a portion of a Random Access Memory (RAM) configured as an overlay RAM. The one or more control circuits are configured to transfer overlay code to the overlay RAM via the host interface.

Storage device with rapid overlay access

Apparatuses, systems, methods, and computer program products are disclosed for using a combined parity buffer memory for multiple open blocks of non-volatile memory. A controller is configured to accumulate, to a memory buffer, combined parity data for multiple open blocks of non-volatile memory in response to write operations to the multiple open blocks of non-volatile memory. A controller is configured to determine to close one block of multiple open blocks of non-volatile memory. A controller is configured to generate non-combined parity data for a block of non-volatile memory based on write operations to multiple open blocks of non-volatile memory.

Growing community of inventors

Bengaluru, India

Raghavendra Gopalakrishnan