Qualcomm Incorporated

Raghavendra Dasegowda

Paras Gupta

Parissa Najdesamii

Rajesh Verma

Sundararajan Ranganathan

Satish Raj

Venugopal Sanaka

Kelageri Nagaraj

A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.

Methods and apparatus for congestion-aware buffering using voltage isolation pathways for integrated circuit designs with multi-power domains

A method of reducing the number of hold violations in an integrated circuit comprises: determining a segment, wherein the segment is a connection between a plurality of points; associating at least one path with each segment, wherein the path is a connection of points including a starting point and an endpoint; determining a weight for at least one said segment, wherein the weight is determined by a number of paths associated with the at least one said segment; ranking the segments in a matrix based upon the determined weight associated with at least one of the segments; and inserting a buffer at least one of the segments based upon said ranking.

Segment and bipartite graph based apparatus and method to address hold violations in static timing

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Raghavendra Dasegowda