Intel Corporation

Mbit Wireless, Inc.

Raghavendra Bhat

Bhaskar Patel

Sean J Lawrence

Sean J W Lawrence

Viswanath Dibbur

Pravin Chander Chandran

Raghavendra R

Techniques are provided for processing video frames in a process flow that includes first and second computation engines. In an example, the first engine is an artificial intelligence based computation engine, and the second engine is a heuristics-based computation engine. A sequence of frames of a video includes a first and second frames that are two consecutive frames in the sequence. An analyzer determines whether the second frame has non-redundant information relative to the first frame. In response to the determination, the analyzer selects one of the first or second engine for processing at least a section of the second frame. For example, if the second frame has non-redundant information relative to the first frame, at least the section of the second frame is processed by the first engine. If the second frame does not include non-redundant information, the second frame is processed by the second engine.

Resource optimization based on video frame analysis

Various systems and methods for determining a distance between a master device and a slave device based, at least in part, on a received signal strength and based, at least in part, on a time interval including generation of a master ranging symbol and detection of a slave ranging symbol.

Non-synchronized RF ranging

Sorting algorithms are generally used at different steps in data processing. In many situations, the efficiency of the sorting algorithm used determines the throughput/execution speed of the application. Methods for implementing high speed sorting in hardware are often based on Batcher's Odd/Even sort or Bitonic sort algorithms. These algorithms are computation intensive and involve high number of logic gates to implement and high power consumption. The higher the number of logic gates, the more silicon area may be required and may lead to higher cost. Insertion sort is a sorting algorithm that is relatively simpler and may require fewer logic gates to implement. However, throughput achieved using Insertion sort algorithm is much lower than the throughput achieved using high speed sorting algorithms. A method and apparatus enable an efficient hardware design capable of simultaneously sorting multiple data inputs for high throughput at reduced complexity.

Method and apparatus for high speed streaming sorter

Spatial Multiplexing (SM) with Multiple Input Multiple Output (MIMO) is used in many communication systems for providing high data rates. While SM-MIMO is a powerful technique for increasing the data rate and bandwidth efficiency, the decoders for SM-MIMO are highly complex. The complexity grows exponentially for optimum decoders as the number of multiplexed layers in SM-MIMO increases. Many reduced complexity suboptimal methods are used in practice that have close to optimum performance but they remain highly complex causing high power consumption which is not desirable for battery operated client terminals. Due to the parallel architecture of many of the SM-MIMO decoders, they involve computations that may eventually turn out to be redundant. A method and apparatus may include identifying and eliminating potentially redundant computations in SM-MIMO decoders based on the technique referred herein as precomputation. The removal of redundant computations enables reduced power consumption for SM-MIMO decoders.

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Bengaluru, India

Raghavendra Bhat