Intel Corporation

Other

Raghavan Sudhakar

Kamal J Koshy

Ravi Kolagotla

Veerendra Bhora

Prasad Modali

Ryo Inoue

Efficiency of computation of logarithmic and exponential functions may be improved using multiplication by pre-computed coefficients to obtain intermediate products.

Computation of logarithmic and exponential functions

In general, in one aspect, the disclosure describes a unified simplified maximum likelihood detector to be utilized with multiple input multiple output (MIMO) receivers to estimate transmitted signals. The unified detector includes a common framework capable of being utilized for multiple detection modes and multiple MIMO configurations.

Unified multi-mode receiver detector

Embodiments of an iterative decoder with early-exit condition detection and methods for decoding are generally described herein. Other embodiments may be described and claimed. In some embodiments, a first codeword is generated from decoded bits after one or more half-iterations of an iterative decoder, a second codeword from decoded bits after an additional half-iteration of the iterative decoder, and the first and second codewords are compared to determine whether the decoded bits are valid. In some embodiments, double or triple codeword matching is selected based on an estimated signal-to-noise ratio (SNR) and the modulation level.

Iterative decoder with early-exit condition detection and methods for decoding

Embodiments of encoding input data into parity data in mechanisms are described generally herein. Other embodiments may be described and claimed.

Efficient CTC encoders and methods

Apparatus, system, and method for scalable traceback techniques for channel decoding are described.

Scalable traceback technique for channel decoder

In one embodiment, a modulo addressing unit for a processor is described that includes a plurality of adders to generate an uncorrected target module address and at least one corrected target module address in parallel. A comparator selects one of the target module addresses a function of a base address (b) for a circular buffer, a length (L) of the circular buffer, an index address (I) and a modifier value (M). In one embodiment the comparator selects a first corrected target module address when I&plus;M<B, a second corrected target module address when I&plus;M>&equals;B&plus;L and an uncorrected module address when B<&equals;I&plus;M<B&plus;L.

Growing community of inventors

Austin, TX, United States of America

Raghavan Sudhakar