Apple Inc.

Raghava Rao V Denduluri

Ajay Bhatia

Vivekanandan Venugopal

Suparn Vats

Suresh Balasubramanian

Gopinath Venkatesh

Teng Wang

Shingo Suzuki

Pradeep Kanapathipillai

Richard F Russo

Rajat Goel

Matthew R Johnson

Edvin Catovic

Pankaj Lnu

An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

Hybrid pulse/two-stage data latch

Hybrid pulse/master-slave data latch

A processor includes an instruction issue circuit, and high-utilization and low-utilization execution unit circuits coupled to execute instructions received from the instruction issue unit. On average, utilization of the low-utilization execution unit circuit is lower than utilization of the high-utilization execution unit circuit. The processor also includes a retention circuit coupled to a different power domain than the low-utilization execution unit circuit, and a power management circuit. The power management circuit may be configured to detect that inactivity of the low-utilization execution unit circuit satisfies a threshold inactivity level; upon detecting that the threshold inactivity level is satisfied, cause architecturally-visible state of the low-utilization execution unit circuit to be copied to the retention circuit; and subsequent to copying of the architecturally-visible state to the retention circuit, cause the low-utilization execution unit circuit to enter a power-off state, where the retention circuit retains stored data during the power-off state.

Execution unit power management

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Cupertino, CA, United States of America

Raghava Rao V Denduluri