Xilinx, Inc.

Ragahavendar M Rao

Kaushik Barman

Parag Dighe

In one embodiment, a matrix multiplication circuit is provided. The circuit includes a plurality of systolic arrays, a pre-processing circuit, and a post-processing circuit. The pre-processing circuit is configured to receive first and second input matrices, and decompose the first input matrix into a plurality of sub-matrices. The pre-processing circuit inputs each of the plurality of sub-matrices to at least a respective one of the plurality of systolic arrays for multiplication with the second input matrix. The post-processing circuit is configured to combine output of the systolic arrays into a result matrix.

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Austin, TX, United States of America

Ragahavendar M Rao