Zoran Corporation

Oren Semiconductor Ltd.

Oren Semiconductor Ltd., Israeli Company

Rafi Retter

Yonatan Manor

David Bar

Noam Galperin

Ram B Friedlander

Alexander Genusov

Peter Feldman

Ariel Zohar

Vlad Fruchter

Ricardo Jaliff

Shlomo Mahlab

Ronny Aboutboul

Asaf Mohr

Rami Friedlander

A system and method for enhancing the reception of a single carrier signal. The single carrier signal includes periodic training signal and data. The system includes a transmitter configured such that L symbols of either the beginning or end of the N symbols of the training signal, where L&#x3c;N, are duplicated at either the end or the beginning of the training signal, respectively. The system further includes a receiver configured to receive the modified training signal for the calculation of FIR coefficients in a single pass and without the need for least mean square (LMS) methods or the like.

Training signal in a single carrier transmission

An enhanced digital signal processor (EDSP) includes execution section that includes the following constituents: a processor, an arithmetic logic unit (ALU), a memory device for holding set of instructions for execution selected from enhanced set of instructions, a memory device for holding data, another clock generator for generating a plurality of clock signals coupled to above constituents. Internal communication bus coupled to the above constituents for affording controlled communication between them, a correlator, coupled to the bus, for communication with the execution section. The correlator having an input port for receiving external input data and an output port for outputting data. The correlator being controlled by the processor and being responsive to the selected instruction from the enhanced set of instructions, for operating in the following mode: correlator processing mode wherein the correlator receives data from the above constituents and outputs data to the constituents, and wherein the input data received through the input port, is transmitted to the output port in an intact form.

Enhanced DSP apparatus

In a composite video signal that contains an image field having vertical synchronization (V.sub.-- Sync) pulses, The V.sub.-- sync pulses include first equalization pulses of E.sub.1 waveforms followed by a serration pulses of S waveforms, T.sub.S -long each, followed by a second equalization pulse of E.sub.2 waveforms, T.sub.E -long each. The transition from a last waveform of the E.sub.1 waveforms to a first waveform of the S waveforms constitutes a vertical synchronization (V.sub.-- sync) signal. The system a reference event occurring at a first time interval .DELTA.T .sub.1 .+-.Er after said V.sub.-- sync signal, wherein Er stands for time shift error. The system includes filter for filtering the composite video signal so as to obtain a filtered signal. Clamper for clamping the filtered signal so as to obtain a clamped signal. First detector for detecting N (N.ltoreq.S) waveforms in the serration pulses thereby indicating first event occurrence. Second detector for detecting M (M.ltoreq.E.sub.2) waveforms in the second equalization pulses, thereby determining the reference event occurrence, such that the .DELTA.T .sub.1 equals M*T.sub.E +S*T.sub.S.

Sync signal separator apparatus

Multiple special purpose processing units are provided in a vector signal processor for concurrent, parallel processing, particularly of complex vectors. The principal processing units are an execution unit, a data movement unit, a control/register unit, a vector buffer unit, an instruction fetch unit, and a bus interface unit.

Architecture for integrated concurrent vector signal processor

A discrete cosine transform/inverse discrete cosine transform or DCT/IDCT integrated circuit capable of performing both DCT and IDCT, includes a processor for processing DCT/IDCT data including, input buffer and arithmetic logic unit for processing incoming data and first pass processed data, multiplier and accumulator unit for performing mathematical operations on DCT/IDCT data, and output buffer and arithmetic logic unit for processing first pass processed data and outgoing data. Also provided is an interleaved random access memory for storing DCT/IDCT data during various stages of processing.

Recycling DCT/IDCT integrated circuit apparatus using a single

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Haifa, Israel

Rafi Retter