Trw Limited

Northrop Grumman Systems Corporation

Raffi N Elmadjian

George L Kerber

Lynn A Abelson

Eric G Ladizinsky

Harvey Newell Rogers

Edwin W Sabin

A method () for etching a through via () on a wafer () of semiconductor material (), wherein the wafer () has a front side surface () and a backside surface (), is described. A layer of photoresist material () is applied to the backside surface (). The layer of photoresist () is then exposed to a light source through a mask having a pre-selected pattern, wherein the developed photoresist is removed to form at least one via () in the remaining photoresist layer (). The remaining photoresist layer () is then baked in order to form a hardened, remaining photoresist layer (). The semiconductor material 102 adjacent to the at least one via () is then gas plasma etched to form a through via () between the backside surface () and the front side surface (). The hardened, remaining photoresist layer () is then removed and a layer of conductive material () is then applied to the surface of the through via () to establish electrical connectivity between the backside surface () and the front side surface ().

Wafer etching techniques

A plasma photoresist hardening technique is provided to improve the etch resistance of a photoresist mask . The technique involves the formation of a thin passivation layer on the photoresist mask which substantially slows down the etching rate of the photoresist material . Advantageously, this technique allows preservation of critical dimension features such as via hole openings and transmission lines. The technique hardens the surface of the photoresist film by both chemically and physically bonding halogenated hydrocarbons with cross linked photoresist polymer. This results in a passivation layer which is highly resistant to harsh plasma etch environments.

Method for plasma hardening photoresist in etching of semiconductor and superconductor films

A method for fabricating an integrated circuit which reduces steps in the integrated circuit comprising the steps of depositing a first conductive material layer over the first dielectric material layer and patterning the first conductive material layer to form a first conductive pattern. A second dielectric layer is then deposited over the first conductive pattern and the exposed portions of the first dielectric material layer. A planarizing material layer is applied over the second dielectric material layer and cured such that the planarizing material layer produces a substantially planar top surface. The planarizing material layer and portions of the second dielectric material layer are removed in a manner which maintains the substantially planar top surface until only a preselected amount of material remains over the first conductive pattern.

Method for fabricating a microelectronic integrated circuit with improved step coverage

A high-temperature (10 K) superconductive integrated circuit has a ground plane (,), an interlevel dielectric (,), and a low value resistor (,) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (,) connected between interconnect wires (,) to produce a desired resistance with a short distance between the interconnect wires (,), thereby significantly reducing the circuit area. A method of fabricating the integrated circuit includes depositing the interlevel dielectric (,) on the ground plane (,) in separate steps, depositing and etching the trilayer (,), etching the low value resistor (,) on the dielectric (,), depositing the high value resistor (,) at substantially the same level above the ground plane (,) as the interconnect wires (,) of the first wire layer (,), and etching the interconnect wires (,) of the second wire layer (,) on the high value resistor (,).

Low inductance superconductive integrated circuit and method of fabricating the same

A high-temperature (10 K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area. A method of fabricating the integrated circuit includes depositing the interlevel dielectric (6) on the ground plane (2) in separate steps, depositing and etching the trilayer (12, 14, 16), etching the low value resistor (18) on the dielectric (6), depositing the high value resistor (20) at substantially the same level above the ground plane (2) as the interconnect wires (22) of the first wire layer (24), and etching the interconnect wires (34) of the second wire layer (32) on the high value resistor (20).

Low inductance superconductive integrated circuit and method of

A high-temperature (10K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area. A method of fabricating the integrated circuit includes depositing the interlevel dielectric (6) on the ground plane (2) in separate steps, depositing and etching the trilayer (12, 14, 16), etching the low value resistor (18) on the dielectric (6), depositing the high value resistor (20) at substantially the same level above the ground plane (2) as the interconnect wires (22) of the first wire layer (24), and etching the interconnect wires (34) of the second wire layer (32) on the high value resistor (20).

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Arcadia, CA, United States of America

Raffi N Elmadjian