Stmicroelectronics S.r.l.

Stmicroelectronics (Grenoble 2) Sas

Stmicroelectronics S.a.

Stmicroelectronics (Grenoble) Sas

Stmicroelectronics (Rousset) Sas

Raffaele Guarrasi

Giuseppe Guarnaccia

Riccardo Locatelli

Michael Soulie

Giuseppe Maruccia

Valerio Catalano

Francesco Giotta

Hajer Ferjani

Radhia Kacem

A method comprising: receiving a transaction associated with an address and having a transaction destination, said address being in an interleaved region of a memory; determining one of a plurality of destinations for said transaction, different parts of said interleaved memory region being respectively accessible by said plurality of destinations; and associating routing information to said transaction, said routing information associated with the determined destination.

Method and apparatus for supporting the use of interleaved memory regions

An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.

Method and apparatus for use with different memory maps

A method includes setting a first indicator to a first value, which causes an apparatus to stop receiving traffic from a traffic source. At least one register is accessed to read or write at least one new value, and a second indicator is set indicating that accessing of the at least one register has completed. The first indicator is set to a second value. When the first indicator has the second value and the second indicator is set, the apparatus is again allowed to receive traffic from the traffic source.

Method and apparatus for supporting reprogramming or reconfiguring

A synchronization system includes a memory and a control circuit. The control circuit includes a write interface for writing data in said memory with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write command, a read interface for reading data from said memory with a second clock signal, wherein the read interface is configured for operating with a read pointer in response to a read command, a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency, and an elaboration circuit for elaborating data in memory with an elaboration latency, wherein the elaboration latency is smaller than the synchronization latency.

Synchronization system and related integrated circuit

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Grenoble, France

Raffaele Guarrasi