Micron Technology Incorporated

Micro Technology, Inc.

Raffaele Bufano

Tommaso Zerilli

Sandra Lospalluti

Paolo Rolandi

Stefano Andreoli

Violante Moschiano

Mirko Scapin

Andrea Giovanni-Xotta

Poorna Kale

Chris Bueb

Marco Gibilaro

A memory device includes a plurality of data lines, a common source, and control logic. The control logic is configured to implement a seed operation by biasing each of the plurality of data lines to a first voltage level with the common source biased to a second voltage level lower than the first voltage level. With each data line biased to the first voltage level, the control logic is configured to float each data line and bias the common source to the first voltage level such that the bias of each data line is boosted above the first voltage level due to capacitive coupling between each data line and the common source.

Seed operation for memory devices

Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device.

Non-volatile configuration for serial non-volatile memory

Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device.

Execute-in-place mode configuration for serial non-volatile memory

A method and a memory device are provided for accessing a storage location. The method includes storing an extended address value in a register in a non-volatile memory device. The method further includes subsequently receiving multiple addresses and combining the stored extended address value with each of the multiple received addresses to produce multiple combined addresses. The method further includes accessing multiple storage locations within the non-volatile memory device based, at least in part, on the multiple combined addresses.

Enhanced addressability for serial non-volatile memory

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Tremestieri Etneo, Italy

Raffaele Bufano