Kepler Computing Inc.

Intel Corporation

Sony Group Corporation

Google Inc.

Sony Corporation

Intel Corporationn

Rafael Rios

Sasikanth Manipatruni

Amrita Mathuriya

Rajeev Kumar Dokania

Ikenna Odinaka

Kelin J Kuhn

Seiyon Kim

Jack T Kavalieros

Gilbert W Dewey

Annalisa Cappellani

Stephen M Cea

Van H Le

Willy Rachmady

Nabil Imam

Tahir Ghani

Martin D Giles

Anand S Murthy

Ramamoorthy Ramesh

Robert Menezes

Benjamin Chu-Kung

Mark Armstrong

Ian A Young

Niloy Mukherjee

Noriyuki Sato

Somilkumar J Rathi

Abhijit Jayant Pethe

Tanay Gosavi

Titash Rakshit

Marko Radosavljevic

Uygar E Avci

Mauricio Manfrini

Brian S Doyle

Peter Chang

Debo Olaosebikan

Shriram Shivaraman

Anurag Chaudhry

Abhishek A Sharma

Ashish Agrawal

Roza Kotlyar

Neal Reynolds

Thomas D Linton, Jr

Robert S Chau

Matthew V Metz

Harry Gomez

Darshak Doshi

Suman Datta

Glenn A Glass

Scott A Hareland

Marc C French

Tom Linton

Fahmida Ferdousi

Seung Hoon Sung

Aaron D Lilak

Kevin Lai Lin

Sanaz Kabehie Gardner

Yih Wang

Daniel Henry Morris

Cory E Weber

Brian E Roberds

Gopinath Bhimarasetti

Patrick H Keys

Aaron A Budrevich

Raseong Kim

Chytra Pawashe

Kent Millard

Ryan E Arch

Mark Stettler

Sivakumar Mudanai

Borna Obradovic

Mayank Sahni

Ravi Pillarisetty

Uday Shah

Muhammad M Khellah

Rishabh Mehandru

Prashant Majhi

Elijah V Karpov

Cheng-Ying Huang

Charles Augustine

James M Powers

Justin R Weber

Somnath Paul

Daniel Pantuso

Lei Jiang

Sherry R Taft

Sanaz Kabehie

Mesut Meterelliyoz

Aura Cecilia Davila Latorre

Edwin B Ramayya

Asynchronous full-adder circuit is described. The full-adder includes majority and/or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and/or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit. Asynchronous full-adders coupled in series is used to implement a carry-ripple adder.

Asynchronous full-adder with majority or minority gates to generate carry-out true output

Asynchronous full-adder with majority or minority gates to generate carry-out false output

Asynchronous full-adder with majority or minority gates to generate sum false output

A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

Ferroelectric or paraelectric wide-input minority or majority gate based low power adder

FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.

Field effect transistors with a gated oxide semiconductor source/drain spacer

A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

Methods of fabricating planar capacitors on a shared plate electrode

Capacitor devices with shared electrode and methods of fabrication

A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Integration methods to fabricate internal spacers for nanowire devices

Drain coupled non-linear polar material based capacitors for memory and logic

Methods of fabricating trench capacitors on a shared plate electrode

A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

Multi-cycle reset mechanism for a chain of majority gates having non-linear polar material

An apparatus and configuring scheme where a capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.

Stacked non-planar capacitors based multi-function linear threshold gate with input based adaptive threshold

Integration of 2T-C for memory and logic applications

An apparatus and configuring scheme where a paraelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the paraelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.

Multi-function threshold gate with input based adaptive threshold and with stacked non-planar paraelectric capacitors

Planar capacitors with shared electrode and methods of fabrication

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Portland, OR, United States of America

Rafael Rios