Massachusetts Institute of Technology

Other

Sony Corporation

Rafael Reif

Takashi Noguchi

Julie Tsai

Andrew J Tang

Anantha P Chandrakasan

Nisha Checka

Andy Fan

Kuan-Neng Chen

Chuan Seng Tan

System and method for analyzing substrate noise is disclosed, which is capable of accepting inputs of increasing complexity and granularity. During the early phases, the tool can accept coarse circuit descriptions, such as gate level netlists. The tool is capable of generating rudimentary substrate models based on estimated die size, allowing the designer to have an early indication of potential substrate noise issues. During the middle phases, the tool can accept more accurate circuit descriptions, such as a SPICE netlist. A more detailed substrate model can be generated, which considers layout information, thereby allowing the designer to make layout and circuit modifications before the circuit is completed. Lastly, during final verification, the tool can accept an even more accurate netlist, such as a SPICE netlist that includes parasitic capacitance. The tool can also accept a more detailed substrate model and provides the substrate noise analysis necessary to finalize the design.

Substrate noise tool

A method of forming a multi-layer semiconductor structure includes attaching a handle-member to a top surface of a first structure using a first interface. At least one region of a bottom surface of the first structure is etched to form at least a first via-hole for exposing a portion of a first conductive member defined on the first structure. A conductive material is disposed in the first via-hole such that a first end of the conductive material is in electrical communication with the first conductive member and a second end of the conductive material is exposed at the bottom surface of the first structure. A second interface is disposed over at least the second end of the conductive material, which serves as a bonding and/or electrical interface between the first conductive member defined on the first structure and a second structure of the multi-layer semiconductor device structure.

Method of forming a multi-layer semiconductor structure incorporating a processing handle member

A multi-layer integrated semiconductor structure is provided, which includes at least a first semiconductor structure and a second semiconductor structure coupled together via an interface. The interface includes at least a first portion adapted to provide a communication interface between the first semiconductor structure and the second semiconductor structure and at least a second portion adapted to reduce electrical interference between the first semiconductor structure and the second semiconductor structure.

Multi-layer integrated semiconductor structure having an electrical shielding portion

A method of forming a multi-layer semiconductor structure includes providing a first layer of a patterned copper bond film having a first predetermined thickness onto a first surface of a first semiconductor. The method further includes providing a second layer of a patterned copper bond film having a second predetermined thickness onto a first surface of a second semiconductor. The first and second semiconductor structures can be aligned, such that the first and second patterned copper bond films are disposed in proximity. A virtually seamless bond can be formed between the first and second patterned copper bond films to provide the first and second semiconductors as the multi-layer semiconductor structure.

Method of forming a multi-layer semiconductor structure having a seamless bonding interface

The present invention pertains to a high-performance thin film transistor having a gate and an active region, whose active region comprises a poly-Si Ge alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si Ge alloy material and the gate, and a method for fabricating such a high-performance thin film transistor.

High performance poly-SiGe thin film transistor and a method of fabricating such a thin film transistor

High performance poly-si1&minus;xgex thin film transistor and a method of fabricating such a thin film transistor

The present invention pertains to a high-performance thin film transistor having a gate and an active region, whose active region comprises a poly-Si.sub.1 -.sub.x Ge.sub.x alloy material and a channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si.sub.1-x Ge.sub.x alloy material and the gate, and a method for fabricating such a high-performance thin film transistor.

Growing community of inventors

Newton, MA, United States of America

Rafael Reif