Freescale Semiconductor,inc.

Rafael M Vilela

Walter Luis Tercariol

Fernando Zampronho Neto

Sandro A P Haddad

A method with a circuit that includes a memory () coupled to an analog line coverage circuit (). The analog line coverage circuit includes a plurality of buffers (-) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (-) in which each bin cell is coupled to a buffer, a multiplexer (), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter () coupled to the multiplexer and to an output terminal of the analog line coverage circuit. The analog line coverage circuit stores an analog voltage that is representative of a number of occasions that a memory location is accessed, and outputs a signal indicative thereof. A processor (), coupled to the memory and to the analog line coverage circuit, enables the analog line coverage circuit when the processor is in a debug mode.

Code coverage circuitry

A circuit includes a memory () coupled to an analog line coverage circuit (). The analog line coverage circuit includes a plurality of buffers (-) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (-) in which each bin cell is coupled to a buffer, a multiplexer (), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter () coupled to the multiplexer and to an output terminal of the analog line coverage circuit. The analog line coverage circuit stores an analog voltage that is representative of a number of occasions that a memory location is accessed, and outputs a signal indicative thereof. A processor () is coupled to the memory and to the analog line coverage circuit, and the processor enables the analog line coverage circuit when the processor is in a debug mode.

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Campinas, Brazil

Rafael M Vilela