Mentor Graphics Corporation

Other

Bull Sas

Rafael Escovar

Roberto Suaya

Salvador Ortiz

Shrinath Thelapurath

Dusan Petranovic

Sylvain Cohard

The invention relates to a method of checkpointing the working environment of a user () session on a server () comprising a first step () of checkpointing the working environment of a first application of said session, characterized in that it comprises at least one second step () of checkpointing the working environment of a second application of said session different from said first application, and in that said first checkpointing step () and said second checkpointing step () are synchronized with each other such that the checkpointed working environment of the first application and the checkpointed working environment of the second application are coherent with each other.

Method of checkpointing the working environment of a session of a user on a server

Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for instance, a circuit description indicative of the layout of signal wires and ground wires in the circuit is received. The signal wires and the ground wires are grouped into at least a first bundle and a second bundle, wherein the first bundle and the second bundle each comprise a respective signal-wire segment and one or more corresponding ground-wire segments. A representative dipole moment is calculated for the first bundle. Using the representative dipole moment, the mutual inductance between the first bundle and the second bundle is calculated. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing design databases created or modified using any of the disclosed techniques are also disclosed.

Mutual inductance extraction using dipole approximations

Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, for instance, a signal-wire segment of a circuit layout is selected. A predetermined number of return paths are identified for the selected signal-wire segment. The selected signal-wire segment and the identified return paths are further segmented into a plurality of bundles, which comprise signal-wire subsegments and one or more associated return-path subsegments that are parallel to and have the same length as the signal-wire subsegments. Loop inductance values and loop resistance values are determined and stored for the signal-wire subsegments in the bundles for at least one frequency of operation. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.

Extracting high frequency impedance in a circuit design using an electronic design automation tool

Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for example, circuit design information indicative of a first inductor and a second inductor is received. A dipole moment associated with the first inductor is determined, where the magnetic field associated with the dipole moment is representative of magnetic fields created by respective turns in the first inductor. A mutual inductance between the first inductor and the second inductor is determined by determining a magnetic flux of the magnetic field of the dipole moment through surfaces bounded by respective wire segments of the second inductor.

Determining mutual inductance between intentional inductors

A method of optimizing the signal propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, one of the physical parameters defining the wiring layout may be adjusted to create an rlc relationship in the wiring layout that maximizes the signal propagation speed. The physical parameter that is adjusted may be, for example, the wire separation between the signal wire and the ground wires or the width of the ground wires. The disclosed method may also be applied to a wiring layout having multiple branches, such as a clock tree. In this context, a first branch may be optimized using the disclosed method. Downstream branches may then be adjusted so that the impedances at the junction between the branches are substantially equal.

Synthesis strategies based on the appropriate use of inductance effects

Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, at least a portion of a circuit description indicative of a circuit layout is loaded. A signal-wire segment is selected. Loop inductance values and loop resistance values for the signal-wire segment are determined at at least a first frequency of operation and a second frequency of operation. Values for one or more inductance components and one or more resistance components of a broadband representation of the signal-wire segment are computed and stored. In this embodiment, the broadband representation comprises at least one but no more than two parallel-coupled resistance components and inductance components. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.

Growing community of inventors

Grenoble, France

Rafael Escovar