Nxp B.v.

Koninklijke Philips Corporation N.v.

St-ericsson Sa

Raf Lodewijk Jan Roovers

Gian Hoogzaad

Lucien Johannes Breems

Harish Kundur Subramaniyan

Gerard Van Der Weide

Eise Carel Dijkmans

George Anthony Brock-Fisher

Stefan Tertinek

Cicero Silveira Vaucher

Gary Allen Schwartz

Steven Russell Freeman

Fabio Sebastiano

Maristella Spella

Salvatore Drago

Hendrik Van Der Ploeg

Theodore Philip Fazioli

A moving object detector detects a moving object in a channel. The detection comprises the detector receiving a plurality of frames based on a transmitter transmitting a plurality of frames over a channel. One or more channel impulse responses (CIRs) of the channel is determined based on the received plurality of frames. The detector determines a CIR phase for each of the CIRs and a phase signal is formed based on a phase value of the CIR phase for each of the CIRs. The detector compares the phase signal with a target signal and detects the moving object in the channel based on the comparison.

Detecting a moving object based on a phase of channel impulse responses

A method for localizing a wireless node includes synchronizing a respective time reference of a plurality of wideband spectrum-sensing units and a master transceiver. A sensing location of each wideband spectrum-sensing unit is stored in a first memory. Each wideband spectrum-sensing unit stores in a second memory a plurality of time-limited samples of a transmission received from a slave transceiver. The time limit of the transmission is determined by the master transceiver, receiving the transmission. The samples from the second memory are correlated with a corresponding plurality of reconstructed samples stored in the first memory to form a respective power delay profile for each of the of the wideband spectrum-sensing units. A slave location of the slave transceiver is determined by applying a Time Difference Of Arrival method to the respective power delay profiles.

Localization of wireless nodes

A communications system comprising a master-node and a slave-node. The master-node comprising: a GNSS receiver configured to provide a GNSS based time reference signal; a master-timing-reference-calibrator configured to determine a master-timing-reference-calibration-signal, for calibrating the master reference timing circuit, based on the GNSS based time reference signal; and a master-reference-timing-circuit configured to provide a master-clock-signal based on the master-timing-reference-calibration-signal, wherein the master-clock-signal is a clock signal for the master-node; and a master-transmitter configured to determine a master-communications-signal using the master-clock signal. The slave-node comprising: a slave-receiver configured to receive the master-communications-signal from the master-node; a slave-timing-reference-calibrator configured to determine a slave-timing-reference-calibration-signal based on the master-communications-signal; and a slave-timing-reference-circuit configured to provide a slave-clock-signal based on the slave-timing-reference-calibration-signal, wherein the slave-clock-signal is a clock signal for the slave-node.

Communications system

One example discloses a transmission line interconnect, comprising: an antenna coupling surface; a transmission line coupling surface; and a dielectric molding compound electromagnetically coupling the antenna coupling surface to the transmission line coupling surface. Another example discloses a method of manufacture, for a transmission line interconnect, comprising: forming a dielectric molding compound; defining an antenna coupling surface on the dielectric molding compound; and defining a transmission line coupling surface on the dielectric molding compound whereby millimeter wave frequencies received at the antenna coupling surface are electromagnetically coupled to the transmission line coupling surface.

Transmission line interconnect

An apparatus for non-galvanic connection between two electrical circuits is described. A base-unit has an RF power source, a data link and an authentication controller. A contactless unit for communication with a base unit has an RF power receiver, a data link and an authentication controller. The base unit and contactless unit can form a non-galvanic connection to replace conventional connectors, for example in a USB wired bus connection.

Wireless power and data connector

The present invention relates to a circuit and a method for automatic common-mode rejection calibration in a differential conversion system and unbalance compensation for balancing the operation point of a circuit in the signal path and for enhancing the common-mode rejection. The circuit for automatic common-mode rejection calibration in a differential conversion system comprises an analog input stage for an analog input signal (), an analog-digital-converter () for converting an analog signal () into its digital representation (), a digital block () arranged to adapt said digital representation () of a portion of a DC offset of said analog input signal () in accordance with whether said analog input signal () is in a predetermined input range of said analog-digital-converter (), and a digital-analog-converter () arranged in a feedback path () from said digital block () to subtraction means () of said analog input stage for converting a digital signal () into an analog output signal (), wherein said analog output signal () is subtracted from said analog input signal () resulting in said analog signal ().

Automatic common-mode rejection calibration

Pulses are detected in a communications receiver by programming each of a plurality of comparators () with a sampling time point selected from a plurality of sampling time points () and with a reference level selected from a plurality of reference levels (). The received signal is applied to each of the comparators such that each of the comparators produces a respective output signal based on a comparison between the received signal level and the selected reference level at the selected sampling time point. The combinations of sampling time points and reference levels can be selected based on knowledge about the expected arrival times of the pulses, and based on knowledge about the possible shapes of said pulses, with the result that the device can detect received pulses without requiring large amounts of hardware, in a device which has an acceptable power consumption. The communications system may be a signaling system, or a radar or positioning system.

Pulse detection in wireless communications system

In a receiver architecture, for example for use in receiving pulses in an Ultra Wideband system, a received signal is applied to a mixer, together with pulses which correspond to expected received pulses. The mixer output is applied to a block, which can be configured either as an integrator or as a filter. When no pulses are being received, this block is configured as a filter, allowing it to lock quickly to any new sequence of pulses, while, when the system has locked to a sequence of pulses, the block is configured as an integrator, so that an improved signal-noise ratio can be achieved.

Reconfigurable pulse detector in wireless communications system

A receive beamformer, and ultrasound system incorporating such a receive beamformer, is constructed to implement multi-bit analog to digital conversion in such a way that the need for gain control in the channel architecture preceding the digital conversion circuitry is obviated. Accordingly, the beamformer and any ultrasound system incorporating it may realize a rigorous level of ADC performance at desirable output rates, and a lower cost. Preferably, the invention construction realizes a level of performance by which CW Doppler may be digitized in the same manner as very wide-band pulsed-wave signals.

Ultrasonic signal acquisition in the digital beamformer

A pipeline/subranging architecture is used to provide a circuit for analog to a digital conversion. A course analog to digital converter, a fine analog to digital to converter, combining logic circuitry and a digital to analog converter are used, together with a voltage to current converter and a current to voltage converter. A residual signal is formed as the difference between the input signal and an output signal of the coarse analog to digital conversion, the latter output signal having been converted to analog form by the analog to digital converter. The residual signal is then scaled appropriately and applied to the fine analog to digital converter. A final output signal is based on the output signals of the coarse digital to analog converter and the fine digital to analog converter.

Analogue to digital converter

An electronic circuit comprising a sample and hold circuit (S/H) for sampling and temporarily holding an input data signal (U , I ), comprising means (S; T ) for the sampling of a data voltage (U ) which corresponds to the input data signal (U , I ), a capacitive element (C ) for temporarily holding the sampled voltage (U ), and means (CPR) for compressing the voltage range of the data voltage (U ) which is to be sampled. The electronic circuit is further provided with expansion means (EXP) for converting the sampled voltage (U ) into a sampled output data signal (I ) in a manner such that it corresponds linearly to the input data signal (U , I ). This is achieved, for example, by using a first field effect transistor (T ) for the compression means (CPR) and a second field effect transistor (T ) for the expansion means (EXP). The gate-source voltage of the first field effect transistor (T ) forms the data voltage (U ) which is compressed since the drain-source current of the first field effect transistor (T ) is linear with respect to the input data signal (U , I ). The first (T ) and second (T ) field effect transistors in fact form a sample and hold current mirror. Thus, though the output current of the sample and hold current mirror is approximately linear with respect to the input current, the output current is a sampled version of the input current.

Sample and hold circuit with compression and expansion

A track and hold amplifier for use in analog/digital-converters comprises, in succession, an input buffer, a pn-junction switch and hold a capacitor. A feedback is provided between the hold capacitor and the input buffer and a second pn-junction switch is provided to disable the feedback during the hold mode.

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Eindhoven, Netherlands

Raf Lodewijk Jan Roovers