Entropic Communications, Inc.

Raed V Moughabghab

Branislav A Petrovic

Michael Scott

Michael William Landry

Edward Warner

An integrated circuit voltage regulator includes a transconductor first stage; and a negative impedance cancellation stage, where the negative impedance cancellation stage comprises cross-coupled transistors at outputs of said transconductor first stage, and resistors in the transconductor first stage and the negative impedance cancellation stage introduce zeros in a transfer function, compensating for parasitic poles. The resistors may compensate for parasitic capacitance inherent in transistors. Load transistors may be coupled to outputs of the transconductance first stage. The voltage regulator may be implemented in a Complementary Metal-Oxide-Semiconductor (CMOS) structure, which may be a system-on-chip integrated circuit. The voltage regulator may provide immunity to power supply noise. The negative impedance cancellation stage may include differential input transistors coupled to the cross-coupled transistors.

High unity gain bandwidth voltage regulation for integrated circuits

An integrated circuit voltage regulator uses a simple CMOS structure to implement a High Unity Gain BandWidth voltage regulator providing for low voltage ripple at the output of the regulator up to high frequencies in the hundreds of MHz range. A transconductor first stage is followed by an impedance cancellation second stage allowing DC gain to be set completely independently of the bandwidth.

Methods and systems for integrated circuit design using dynamic voltage scaling may comprise (a) designing an IC to meet a voltage dependent frequency specification, the IC design including feedback circuitry for controlling a power supply voltage to a fabricated instance of the IC design, (b) characterizing a fabrication process for corner lots for the IC design at a range of power supply voltage levels achievable by the feedback circuitry; (c) validating the IC design against the fabrication process if the frequency specification is achievable for essentially all instances of the IC design fabricated, wherein the feedback circuitry in each IC resulting from the IC design is operable to respectively adjust the power supply voltage of each IC resulting from the IC design by reducing the power supply voltage if the IC is from a fast corner lot and increasing power supply voltage if from a slow corner lot.

Integrated circuit design using dynamic voltage scaling

A method and an apparatus from such method for designing an integrated circuit (IC) that mitigates the effects of process, voltage, and temperature dependent characteristics on the fabrication of advanced IC's but provides high die yields, lower power usage, and faster circuits. Conventional design process takes into account power supply voltage Vdd as a variable that must be considered in a skewed corner analysis. The disclosure teaches that the IC design process can be substantially simplified by essentially factoring out voltage based variations in corner lot analysis for IC designs that include dynamic voltage scaling circuitry, because each fabricated IC die of an IC design having dynamic voltage scaling can individually adjust the applied supply voltage Vdd within a range to offset local process-induced variations in the performance of that specific IC die.

The terminating impedance of a networked device in a wired communication channel is controlled to avoid an impedance discontinuity when power is applied and removed from the node or other event occurs that would change the impedance of the signal interface. When the node transmits or receives signals using the communication channel, the transmit or receive device presents a matched termination to the channel. When power is removed or the device is reset, the transmit and receive circuitry is not operational and the matched impedance is therefore maintained by a separate device. The impedance may be varied slowly from a match to a high impedance to allow other devices in the network to adapt to the change in multipath environment that results from the impedance change. Alternatively, the signal interface can be switched to a passive static impedance that is maintained while power is off or the disrupting event occurs.

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San Diego, CA, United States of America

Raed V Moughabghab