Freescale Semiconductor,inc.

University of Rochester

Other

Nxp Usa, Inc.

Nxp B.v.

Radu Mircea Secareanu

Olin L Hartin

Eby G Friedman

Suman K Banerjee

Bernhard Grote

Michael A Stockinger

Enrique Ferrer

Qiang Li

Dolphin Abessolo Bidzo

Michael J Zunino

Sandra J Wipf

Sateh Jalaleddine

Mikhail Popovich

Detlef Clawin

Emre Salman

Janusz Tomasz Klimczak

An encryption/decryption method is disclosed, where the input data string is described in term of consecutive groups of alternating same type bits, where one of these groups of same type bits is defined as a preferred group with the other groups having either lower or higher number of same type bits, where the data string is partitioned into variable length processing strings where the variable length is determined by the occurrence of the preferred group or of a determined number of bits consisting of groups of lower number of same type bits, where these variable length processing strings are encrypted function of the configuration and content of each processing string only, where consecutive processing strings are additionally encrypted based on their content only, where further encryption is performed from permutations of select partitions of groups of processing strings only as well as from permutations of select partitions of consecutive processing strings, where all said encryption means creating a total encryption space, where this total encryption space is represented by a multitude of encryption keys, where each of said encryption keys is interpreted using a set of reference data, and where communication between a data sender device and a data receiver device is secured by conforming to device specific settings.

Binary encryption / decryption method for secure audio / video broadcast and communication and for data transmission / storage

A binary data compression/decompression method is disclosed, where any input binary data string (IFDS) is uniquely and reversibly compressed/decompressed without any data loss, by first transforming the IFDS in well defined variable length binary constructs using well defined criteria and procedure, followed by partitioning the IFDS in IFDS slices of optimal sizes based on well defined criteria, where each IFDS slice is individually compressed according to three independent schemes and several extensions that are all based on mathematical description of well defined relationships noted within the content of such an IFDS slice in term of specific binary constructs, leading to unique identifiable binary entities that are used to generate compression gain by reassignment of specific well defined parts of the data constructs within the subject IFDS slice, where such compressed IFDS slices are assembled in the same original slice order as found in the original uncompressed IFDS, creating the full compressed IFDS, where an unlimited but defined number of such compression cycles are executed until the desired final file size is achieved.

Binary compression / decompression method

A binary data compression/decompression method is disclosed, where any input binary data string (IFDS) is uniquely and reversibly compressed/decompressed without any data loss by first uniquely formatting and fully describing the IFDS using a set of well defined binary constructs, followed by creating complex structures from custom combinations of said binary constructs that occur within the arbitrary IFDS content, wherein the choice of the said custom combinations depend on the said IFDS content in term of binary constructs therefore creating IFDS content variations and distributions from an expected nominal base wherein said variations and distributions reflect the actual content of the arbitrary IFDS, followed by uniquely processing these variations and distributions in content using several schemes where each scheme brings a unique compression feature, and wherein once this processing completes (i.e. the end of the arbitrary IFDS is reached), it is called that the end of one compression cycle is reached, and wherein another compression cycle can be applied to the data by repeating the cycle steps, and where such compression cycles are repeated until the desired compressed file is reached or until a file floor size limit is reached, floor size below which the disclosed compression has limitations.

Binary data compression / decompression method

A hardware implementable lossless data compression decompression algorithm is disclosed, where the input data string is described in term of consecutive groups of alternating same type bits, where one of these groups of same type bits is defined as a preferred group with the other groups having either lower or higher number of same type bits, where the data string is partitioned into variable length processing strings where the variable length is determined by the occurrence of the preferred group or of a determined number of bits consisting of groups of lower number of same type bits, where these variable length processing strings are processed function of the configuration and content of each processing string only, where consecutive processing strings are additionally processed based on their content only, where processing is performed in a loop until a certain target performance is achieved, where processing is done without any data analysis, and where no negative compression gain is achieved for any content of an input string.

Hardware implementable data compression/decompression algorithm

An electrostatic discharge (ESD) protection scheme is provided that reduces EMI noise propagation among functional circuit blocks of an integrated circuit (IC). Traditional ESD protection schemes include an ESD bus electrically tied to the substrate of an integrated circuit (e.g., a P-well) and substrate well regions associated with electromagnetic interference (EMI) aggressor and sensitive circuits. These electrical couplings can propagate EMI noise on the ESD bus throughout the circuit blocks of the IC. Embodiments provide an ESD bus that is not tied to the substrate well regions associated with EMI aggressor and sensitive circuits of the IC, but instead is a separate conductive layer electrically coupled to an external ground. In this manner, the device circuits are isolated from EMI noise carried in the ESD bus, thereby protecting the various functional blocks from such noise.

Method and system for improved noise isolation in an electrostatic discharge protection scheme

An electrostatic discharge, ESD, protection structure () formed within a semiconductor substrate of an integrated circuit device (). The integrated circuit device () comprising: a radio frequency domain (); a digital domain (). The ESD protection structure () further includes an intermediate domain located between the radio frequency domain () and the digital domain () that comprises at least one radio frequency, RF, passive or active device that exhibits an impedance characteristic that increases as a frequency of operation increases.

Electrostatic discharge protection structure

A device fabricated on a wafer is disclosed. The device includes a first block of the wafer and a second block of the wafer isolated from the first block using a first deep trench isolation (DTI). The device further includes a third block of the wafer isolated from the second block using a second DTI. The second block includes a first vertical section coupled to a first ground, a second vertical section, a third vertical section coupled to a second ground. The second vertical section is doped lightly compared to the first vertical section and the second vertical section.

Device isolation

A structure for improved noise signal isolation in semiconductor devices. In one embodiment, the structure includes a second-conductivity type substrate, a 1first-conductivity type well, a 1first-conductivity type layer, a second-conductivity type layer positioned between the 1first-conductivity type well and the 1first-conductivity type layer. The structure also includes a 2first-conductivity type well, and a 2first-conductivity type layer positioned between the 2first-conductivity type well and the 1first-conductivity type layer. The 1first-conductivity type layer and the second-conductivity type layer are positioned between the P type substrate and the 1first-conductivity type well, and the 1first-conductivity type well is laterally separated from the 2first-conductivity type well.

Structure for improved noise signal isolation

An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.

Noise isolation between circuit blocks in an integrated circuit chip

An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit. The metal ring has a first gap and the ring-shaped region has a second gap.

Integrated circuit chip with discontinuous guard ring

Apparatus and a method are provided for reducing noise in mixed-signal and digital circuits. One apparatus () includes a metal-oxide-semiconductor field-effect transistor (MOSFET) (). MOSFET () includes a doped substrate () with a source formed proximate a substrate tie () and a substrate tie () adjacent substrate (). A ground rail () is coupled to the source and substrate tie (), and a ground rail () is coupled to substrate tie (). Ground rails () and () are configured to be coupled to different ground networks (and). One method includes producing a model of a semiconductor device including a standard semiconductor cell (). The semiconductor cell is identified as a noise-sensitive or a noise-producing semiconductor cell (), and the semiconductor cell is replaced with a corresponding noise-aware semiconductor cell ().

Apparatus and method for reducing noise in mixed-signal circuits and digital circuits

Flip-chip electronic devices () employ bumps () for coupling to an external substrate. Device cells () and bumps () are preferably arranged in clusters () where four bumps () substantially surround each device cell () or form a cross with the device cell () at the intersection of the cross. The bumps () are desirably spaced apart by the minimum allowable bump () pitch (L). Typically, each device cell () contains one or more active device regions () depending on the overall function. Complex devices () are formed by an X-Y array of the clusters (), where adjacent clusters () may share bumps () and/or device cells (). In a preferred embodiment, the bumps () form the outer perimeter () of the device (). The maximum device temperature and overall noise is reduced.

Electronic device with connection bumps

An integrated circuit includes a p-well block region having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region formed surrounding the p-well block region for providing noise isolation between the first circuit block and the second circuit block.

A system-on-chip or other circuit has an on-chip noise-free ground which is added to divert ground noise from the sensitive nodes. An on-chip decoupling capacitor, tuned in resonance with the parasitic inductance of the interconnects, can be provided to add an additional low impedance ground path.

Method and apparatus to reduce noise fluctuation in on-chip power distribution networks

A system-on chip (SOC) () and method of isolating noise in a SOC, including a plurality of noise sensitive circuit blocks () and ESD protected pads (and). A VDD isolation pad () is connected to an N well ring () of the first noise sensitive circuit () to collect noise from the substrate () and isolate the circuit from the P well region (). A ground protected pad () is connected to an isolated P well () of a first noise sensitive circuit (). The ground pad () collects noise from the isolated P well () and sends it to ground. A dedicated ground isolation pad () is connected to a P well ring () of a second noise sensitive circuit (). The dedicated ground isolation pad () collects noise from the P well ring () and sends it to ground. The dedicated ground isolation pad () and the ground pad () collect noise that would normally propagate between the first and second noise sensitive circuits () and additional circuits that share the same substrate ().

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Phoenix, AZ, United States of America

Radu Mircea Secareanu