Excelitas Technologies Singapore Pte. Ltd.

Radu M Marinescu

Hermann Karagoezoglu

Grigore D Huminic

Arthur John Barlow

Philippe Vasseur

Jin Han Ju

Michael Ersoni

Piotr Kropelnicki

Kai Liang Chuan

Reiner Quad

Yuan Hsi Chan

Fred Plotz

An unreleased thermopile IR sensor and method of fabrication is provided which includes a new thermally isolating material and an ultra-thin material based sensor which, in combination, provide excellent sensitivity without requiring a released membrane structure. The sensor is fabricated using a wafer transfer technique in which a substrate assembly comprising the substrate and new thermally isolating material is bonded to a carrier substrate assembly comprising a carrier substrate and the ultra-thin material, followed by removal of the carrier substrate. As such, temperature restrictions of the various materials are overcome.

Unreleased thermopile infrared sensor using material transfer method

A method for manufacturing an imaging device is presented. The method starts with providing a wafer having a membrane with an opening bonded to a substrate. A photoresist layer is deposited over the membrane and wafer surface. A portion of the substrate back surface under a central part of the membrane is etched anisotropicly. A first region of the photoresist layer is removed, exposing an opening in the membrane, so that a first isotropic etching of the substrate is performed through the membrane opening. A second region of the photoresist layer is stripped, exposing a second membrane opening, providing access for a second isotropic etching of the substrate through the first and/or second membrane opening.

CMOS integrated method for the release of thermopile pixel on a substrate by using anisotropic and isotropic etching

A method for manufacturing an imaging device in a semiconductor substrate is disclosed. The substrate includes a first surface, a second surface substantially opposite the first surface, and a thickness defined by a distance between the first surface and the second surface. A trench is fabricated in the semiconductor substrate first surface. A passivation layer is applied over the substrate first surface and the trench, optionally filling the trench by depositing a conformal layer over the substrate first surface. The conformal layer and the passivation layer are planarized from the substrate first surface, and a membrane is fabricated on the substrate first surface. From the substrate second surface, a cavity is formed in the substrate abutting the membrane and at least a portion of the trench via the unmasked region.

CMOS integrated method for fabrication of thermopile pixel on semiconductor substrate with buried insulation regions

A method of manufacturing a pixel structure having an umbrella absorber is disclosed. The method includes providing a substrate with a membrane on a first surface of the substrate. The membrane has one or more openings that expose one or more portions of the first surface, and includes a thermopile. A sacrificial layer is deposited on the membrane and in the one or more openings. The sacrificial layer is patterned to expose a portion of the membrane associated with one or more hot junctions of the thermopile. A rigid, thermally-conductive layer is formed on the sacrificial layer and on the exposed portion of the membrane associated with the one or more hot junctions of the thermopile. An absorber is deposited on the rigid, thermally-conductive layer. A cavity is formed in the substrate from a second surface of the substrate to the membrane and the sacrificial layer is removed.

CMOS integrated method for the fabrication of thermopile pixel with umbrella absorber on semiconductor substrate

A vertically stacked thermopile and an IR sensor using said stacked thermopiles are provided. The vertically stacked thermopile may include multiple thermocouples stacked vertically on one another. The thermocouples may be connected in series, parallel, or a combination of series and parallel. One or more vertically stacked thermopiles may be included in an IR sensor and the thermopiles may be connected in series, parallel, or a combination of series and parallel.

Vertically stacked thermopile

Graphene-based thermopiles are provided. The graphene-based thermopiles may include thermocouples having one or more graphene strips that may be polarized to adjust their Seebeck coefficients. The polarized graphene strips may have larger Seebeck coefficients than the materials conventionally used in thermopile devices. As a result, the graphene-based thermopiles may generate large output voltages using fewer thermocouples than conventional thermopile devices.

Graphene-based thermopile

A thermopile sensor array is provided. The thermopile sensor array may include multiple pixels formed by multiple thermopiles arranged on a single common shared support membrane. A separation between the edge of the shared support membrane and the outermost thermopile(s) may be included to provide additional thermal isolation between the thermopile and an underlying silicon substrate.

Growing community of inventors

Pointe-Claire, Canada

Radu M Marinescu