Kabushiki Kaisha Toshiba

Kioxia Corporation

Radu Berdan

Takao Marukame

Yoshifumi Nishi

Jun Deguchi

Daisuke Miyashita

Kumiko Nomura

According to one embodiment, in a semiconductor integrated circuit, a second switch has a first end connected to a first end of a capacitive element and a second end connected to a node of a reference potential. A third switch has a first end connected to the first end of the capacitive element and a second end connected to an input node of an amplifier circuit. A control circuit maintains the second switch in an on state while maintaining a first and the third switches in an off state in a first period and maintains the first switch in an on state while maintaining the second and third switches in an off state in a second period after the first period. End timings of the second period in the plurality of DA converters are synchronized with each other in response to a signal from a global circuit.

Semiconductor integrated circuit and arithmetic system

According to one embodiment, in a processing circuit of a computation system, a plurality of comparators corresponds to the respective columns, each including a first input node, a second input node, and an output node, the first input node receiving any one of the second signals, the second input node receiving a signal corresponding to a global reference signal provided to each second input node, the output node outputting a local signal. A global circuit is provided common to the plurality of comparators, the global circuit generating a global signal according to a plurality of the local signals, the global circuit generating the global reference signal by an SAR method according to the global signal. The processing circuit disables some of the plurality of comparators according to the local signals and the global signal.

Computation system with a plurality of comparators and a global circuit

A spiking neural network device according to an embodiment includes a synaptic element, a neuron circuit, a synaptic potentiator, and a synaptic depressor. The synaptic element has a variable weight. The neuron circuit inputs a spike voltage having a magnitude adjusted in accordance with the weight of the synaptic element via the synaptic element, and fires when a predetermined condition is satisfied. The synaptic potentiator performs a potentiating operation for potentiating the weight of the synaptic element depending on input timing of the spike voltage and firing timing of the neuron circuit. The synaptic depressor performs a depression operation for depressing the weight of the synaptic element in accordance with a schedule independent from the input timing of the spike voltage and the firing timing of the neuron circuit.

Spiking neural net work device and learning method of spiking neural network device

According to an embodiment, a reinforcement learning system includes a memristor array in which each of a plurality of first direction lines corresponds to one of a plurality of states, and each of a plurality of second direction lines corresponds to one of a plurality of actions, a first voltage application unit that individually applies voltage to the first direction lines, a second voltage application unit that individually applies voltage to the second direction lines, a action decision circuit that decides action to be selected by an agent in a state corresponding to a first direction line to which a readout voltage is applied, a action storage unit that stores action selected by the agent in each state that can be caused in an environment, and a trace storage unit that stores a time at which the state is caused by action selected by the agent.

Reinforcement learning system

An arithmetic apparatus according to an embodiment outputs a multiplicative value obtained by multiplying a weight value and an input value. The arithmetic apparatus includes a memristor, a logarithmic transform circuit, and a current-voltage converter circuit. The memristor is a device capable of changing voltage-current characteristic, and the memristor is preset to voltage-current characteristic according to the weight value. The logarithmic transform circuit applies an intermediate voltage, to the memristor, that is obtained by logarithmically transforming an input voltage according to the input value in accordance with a logarithmic transform function obtained by multiplying a natural logarithm function by a preset coefficient. The current-voltage converter circuit outputs an output voltage obtained by performing current-voltage conversion of current flowing through the memristor according to a preset linear function, as a multiplicative value.

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Shinagawa, Japan

Radu Berdan