Nvidia Corporation

Skyera, LLC

Seagate Technology Incorporated

Western Digital Technologies, Inc.

Lsi Corporation

Sandforce, Inc.

Tachyum Ltd.

Google Inc.

Wave Computing, Inc.

Sandisk Technologies Inc.

Radoslav Danilak

Rodney Norman Mullendore

William Henry Radke

Ladislav Steffko

Andrew John Tomlin

Justin Cree Jones

Qi Wu

Pinchas Herman

Sameer Nanda

Anand Rajagopalan

Thomas A Maufer

Paul J Sidenblad

Ashutosh Jha

Paul Gyugyi

Norbert Juffa

Krishnaraj S Rao

Amit Bothra

Arvind Pruthi

Suresh Rajan

Ziyad Sami Hakura

Brian K Langendorf

Brad W Simeral

Michael J S Smith

Stefano A Pescador

Samit Chaudhuri

Earl T Cohen

Robert Anthony Alfieri

Hao Zhong

Yan Li

Christopher John Nicol

Guiqiang Dong

John R Nickolls

Rui Manuel Bastos

Ross John Stenfort

Karim Abdalla

Guangming Lu

Dmitry Vyshetsky

Jui-Yao Yang

Lordson L Yue

John W Berendsen

Nolan David Goodnight

Leader Ho

Paul J Guygyi

A processor has first, second and third ALUs. The first ALU has on a first side an input and an output. The second ALU has a first side facing the first side of the first ALU, an input and an output on the first side of the second ALU and being in a rotated orientation relative to the input and the output of the first side of the first ALU, and an output on a second side of the second ALU. The third ALU has a first side facing the second side of the second ALU, and an input and an output on the first side of the third ALU. The input of the first side of the first ALU is logically directly connected to the output of the first side of the second ALU.

Arithmetic logic unit layout for a processor

A methodology for populating an instruction word for simultaneous execution of instruction operations by a plurality of ALUs in a data path is provided. The methodology includes: creating a dependency graph of instruction nodes, each instruction node including at least one instruction operation; first selecting a first available instruction node from the dependency graph; first assigning the selected first available instruction node to the instruction word; second selecting any available dependent instruction nodes that are dependent upon a result of the selected first available instruction node and do not violate any predetermined rule; second assigning to the instruction word the selected any available dependent instruction nodes; and updating the dependency graph to remove any instruction nodes assigned during the first and second assigning from further consideration for assignment.

System and method of populating an instruction word

Techniques are described for accessing data from a storage device. In one example, the storage device may include a storage medium comprising non-volatile memory, a network connection, and one or more processing entities. The one or more processors may be configured to receive a request from the network connection at the non-volatile memory storage device for accessing data associated with a file system object, the request comprising a virtual address offset, a file object identifier and a size of the data access, perform, at a flash translation layer of a storage device software stack executing on the one or more processing entities of the storage device, a translation from the virtual address offset to a physical address for the data stored on the non-volatile memory, using the virtual address offset and the file object identifier, and access the data from the physical address from the storage medium.

Address translation for storage device

A methodology for populating multiple instruction words is provided. The methodology includes: creating a dependency graph of instruction nodes, each instruction node including at least one instruction operation; first assigning a first instruction node to a first instruction word; identifying a dependent instruction node that is directly dependent upon a result of the first instruction node; first determining whether the dependent instruction node requires any input from two or more sources that are outside of a predefined physical range of each other, the range being smaller than the full extent of the data path; and second assigning, in response to satisfaction of at least one predetermined criteria including a negative result of the first determining, the dependent instruction node to the first instruction word.

System and method for populating multiple instruction words

A translation system can translate a request having multiple fields to a physical address using the fields as indexes to a multi-dimensional graph. A field or portion of a field can represent a location along an axis. When combined together, the fields can represent a point in n-space, where n is the number of axes. In some embodiments, a nearest neighbor calculation can be sufficient along an axis. Therefore, a point in n-space defined by the fields can be translated along an axis until a nearest neighbor entry is determined. When the entry is determined, the entry can be accessed to determine a correct response to the translation request.

Apparatus and method for using fields in N-space translation of storage requests

A methodology for creating and executing instruction words for simultaneous execution of instruction operations is provided. The methodology includes creating a dependency graph of nodes with instruction operations, the graph including at least a first node having a first instruction operation and a second node having a second instruction operation being directly dependent upon the outcome of the first instruction operation; first assigning the first instruction operation to a first instruction word; second assigning a second instruction operation: to the first instruction word upon satisfaction of a first at least one predetermined criteria; and to a second instruction word, that is scheduled to be executed during a later clock cycle than the first instruction word, upon satisfaction of a second at least one predetermined criteria; and executing, in parallel by the plurality of ALUs and during a common clock cycle, any instruction operations within the first instruction word.

System and method for creating and executing an instruction word for simultaneous execution of instruction operations

The present disclosure relates to examples of reducing memory write operations using coalescing memory buffers. In one example implementation according to aspects of the present disclosure, a method comprises computing a difference between a current state of data of at least one block of a storage device to which data is to be written and a state that would result from a write operation. The method further comprises populating at least one coalescing memory buffer with difference information associated with the difference and to be used to update an associated block of the storage device.

Techniques for reducing memory write operations using coalescing memory buffers and difference information

A plurality of software programmable processors is disclosed. The software programmable processors are controlled by rotating circular buffers. A first processor and a second processor within the plurality of software programmable processors are individually programmable. The first processor within the plurality of software programmable processors is coupled to neighbor processors within the plurality of software programmable processors. The first processor sends and receives data from the neighbor processors. The first processor and the second processor are configured to operate on a common instruction cycle. An output of the first processor from a first instruction cycle is an input to the second processor on a subsequent instruction cycle.

Reconfigurable interconnected programmable processors

The present disclosure relates to examples of controlling recycling of blocks of memory. In one example implementation according to aspects of the present disclosure, a method comprises allocating at least one block of memory selected from a subset of blocks to be written in accordance with an equalizing technique to equalize a variation between blocks of memory based on at least one factor. The method further comprises resupplying the subset of blocks.

Techniques for controlling recycling of blocks of memory

Address translation for a non-volatile memory storage device

Methods, systems and computer-readable storage media for increasing spare space in a storage subsystem including a flash memory, extending a lifetime of the storage subsystem to achieve a stored selected minimum lifetime based at least in part as a result of the increasing spare space, and identifying at least one aspect associated with the lifetime of the storage subsystem. The storage subsystem may include compressed data stored in the flash memory.

System, method, and computer program product for increasing spare space in memory to extend a lifetime of the memory

A translation system can translate a storage request to a physical address using fields as keys to traverse a map of nodes with node entries. A node entry can include a link to a next node or a physical address. Using a portion of the key as noted in node metadata, a node entry can be determined. When adding node entries to a node, a node utilization can exceed a threshold value. A new node can be created such that node entries are split between the original and new node. Node metadata of the parent node, new node and original node can be revised to identify which parts of the key are used to identify a node entry. When removing node entries from a node, node utilization can cross a minimum threshold value. Node entries from the node can be merged with a sibling, or the map can be rebalanced.

Apparatus and method for insertion and deletion in multi-dimensional to linear address space translation

Growing community of inventors

Cupertino, CA, United States of America

Radoslav Danilak