Xilinx, Inc.

Asm International N.v.

Radko Gerard Bankras

Michael J Hart

Martin L Voogel

James Karp

Kameswara K Rao

Shahin Toutounchi

Kevin T Look

Daniel Gitlin

Albert Hasper

Gert-Jan Snijders

Jongheon Jeong

Marinus J De Blank

Lieve Vandezande

Titanium nitride (TiN) films are formed in a batch reactor using titanium chloride (TiCl) and ammonia (NH) as precursors. The TiClis flowed into the reactor in temporally separated pulses. The NHcan also be flowed into the reactor in temporally spaced pulses which alternate with the TiClpulses, or the NHcan be flowed continuously into the reactor while the TiClis introduced in pulses. The resulting TiN films exhibit low resistivity and good uniformity.

Deposition of TiN films in a batch reactor

Chemical vapor deposition of TiN films in a batch reactor

Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.

Non-volatile memory array using gate breakdown structures

Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located &ldquo;on chip&rdquo; with an array of memory cells. These charge pump circuits are preferably fabricated utilizing the same standard CMOS processing techniques that were utilized to form the memory cell structures and related circuitry.

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Enschede, Netherlands

Radko Gerard Bankras