International Business Machines Corporation

Siemens Aktiengesellschaft

Other

Kabushiki Kaisha Toshiba

Infineon Technologies North America Corp.

Infineon Technologies Ag

Radhika Srinivasan

Herbert Lei Ho

Jack Allan Mandelman

Erwin Hammerl

Reinhard J Stengl

Alvin P Short

Rajarao Jammy

Jochen C Beintner

Johnathan E Faltermeier

David M Dobuzinsky

Scott David Halle

Mark A Jaso

Matthias Ilg

Bernhard Poschenrieder

Oleg Gluschenkov

Michael Patrick Chudzik

Gary Bela Bronner

Yun-Yu Wang

Rama Divakaruni

Christopher Carr Parks

Soichi Nadahara

Rajesh Rengarajan

Kenneth T Settlemyer, Jr

Yujun Li

Philip L Flaitz

Ronald Wayne Nunes

Richard L Kleinhenz

Giuseppe La Rosa

Bertrand Flietner

Kathryn H Varian

Farid Agahi

Jeffery L Hurd

Francis G Trudeau

Shigeki Sugimoto

Klaus Roithner

Klaus Penner

Dinah S Weiss

Hirofumi Inoue

Andre R LeBlanc

A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of each sidewall of openings. A method for fabricating the above-mentioned 3D microelectronic structure is also provided. Specifically, the method includes a step of selectively forming a thermal nitride layer on at least an upper portion of each sidewall of an opening formed in a substrate.

Vertical thermal nitride mask (anti-collar) and processing thereof

A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.

Method and device for array threshold voltage control by trapped charge in trench isolation

A process for forming a small grain structure in a material within a semiconductor device near the interface of an adjacent dissimilar material, to result in a highly diffusive grain structure. The highly diffusive grain structure formed within one material enhances diffusion of a dopant impurity, and provides for improved dopant control in an adjacent dissimilar material.

Dopant control of semiconductor devices

Fabrication of trench capacitors using disposable hard mask

The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.

Method of controllably forming a LOCOS oxide layer over a portion of a

A reduction in parasitic leakages of shallow trench isolation vias is disclosed wherein the distance between the silicon nitride liner and the active silicon sidewalls is increased by depositing an insulating oxide layer prior to deposition of the silicon nitride liner. Preferably, the insulating oxide layer comprises tetraethylorthosilicate. The method comprises of etching one or more shallow trench isolations into a semiconductor wafer; depositing an insulating oxide layer into the trench; growing a thermal oxide in the trench; and depositing a silicon nitride liner in the trench. The thermal oxide may be grown prior to or after deposition of the insulating oxide layer.

Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI

A reduced metal-rich interface between a poly and metal silicide layer is achieved by insitu doping the metal silicide layer.

Insitu doped metal policide

A method for forming a electrically isolated semiconductor devices in a silicon body. A trench is formed in a selected region of the body. A barrier material is deposited over sidewalls of the trench. Portions of the barrier material are removed from a first sidewall portion of the trench to expose such first sidewall portion of the trench while leaving portions of such barrier material on a second sidewall portion of the trench to form a barrier layer thereon. A dielectric material is deposited in the trench, a portion of dielectric material being deposited on the exposed first sidewall portion of the trench and another portion of such deposited dielectric material being deposited on the barrier material. The dielectric material is annealed in an oxidizing environment to densify such deposited dielectric material, the barrier layer inhibiting oxidation of the said second sidewall portion of the trench. A plurality of the semiconductor devices is formed in the silicon body with such devices being electrically isolated by the dielectric material in the trench.

Method for forming electrical isolation for semiconductor devices

Strap resistance, surface strap shorts and wordline capacitance can be reduced by providing a selectively grown silicon strap which tapers away from spacer nitride and has less contact with spacer nitride. In addition the strap is optionally doped with an arsenic implant which reduces resistance.

Reliable low resistance strap for trench storage DRAM cell using

Method for forming three-dimensional device structures comprising a second device having sub-groundrule features formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device. the sub-groundrule feature is formed using mandrel and spacers.

Three-dimensional device layout with sub-groundrule features

In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

Buried strap formation in a DRAM trench capacitor

A method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell. The electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

Buried-strap formation in a dram trench capacitor

Method for forming three-dimensional device structures comprising a second device formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device.

Three-dimensional device layout having a trench capacitor

A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.

Storage node process for deep trench-based DRAM

Growing community of inventors

Mahwah, NJ, United States of America

Radhika Srinivasan