Qualcomm Incorporated

Radhakrishna Mugada

Santhosh Reddy Akavaram

Chintalapati Bharath Sai Varma

Sridhar Anumala

Sai Naresh Gajapaka

Sri Ananda Sai Jannabhatla

Venkatesh Petnikota

Muzaffaruddin Mohammed

Subham Panda

Jyothi Ramidi

Nileshkumar Chandrakantbhai Motawala

Methods and apparatuses directed to improving performance and data integrity within die architectures. In some examples, a die package includes a memory device, and a processor coupled to the memory device. The memory device may serve as a cache for another memory device. The processor receives a signal indicating that a number of errors have been detected. In response to the signal, the processor reads an error count corresponding to each of multiple memory rows of the memory device. Further, the processor determines a first memory row of the memory rows based on the error counts. The processor also determines a second memory row of the memory rows based on access data characterizing memory accesses of the plurality of rows. The processor further writes data stored at the first memory row to the second memory row of the memory device, and disables the first memory row.

Apparatus and methods for memory data integrity within die architectures

This disclosure provides systems, methods, and devices for memory systems that support exception event handling and reporting. In a first aspect, a method of exception event handling in a flash memory system includes a host memory controller receiving a response from the memory system, the response comprising user data, an indication that an exception event was encountered by the memory system, and information regarding the exception event encountered by the memory system; and transmitting an acknowledgement of receiving the indication that the exception event was encountered by the memory system. Other aspects and features are also claimed and described.

Exception event handling in flash memory system

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Hyderabad Telangana, India

Radhakrishna Mugada