Cisco Technology, Inc.

Radesh Manian

Harshad Bhaskar Nakil

Rajashekar Reddy

Hampapur Nagaraj Ajay

Shirish K Sathe

Nipa Kumar

A system and method for improving the speed of packet switching in a routing platform that maps shared I/O memory into two address spaces. The first address space is mapped with the cache attribute and uses the cache write through attribute. Addresses in this address space are not equal to the physical address in the shared I/O memory and are translated to the physical addresses. Code executed by the CPU to switch packets utilizes the first address space to access packet data. The second address space is mapped with the non-cache attribute and addresses in this space are equal to the physical addresses in the shared I/O memory. The second address space is utilized by I/O devices when accessing shared I/O memory. Addresses of buffers for storing packet data in the shared I/O memory are converted from the first address space to the second address space when given to I/O devices.

Algorithm to improve packet processing performance using existing caching schemes

A method and apparatus are described for scheduling traffic in a network. The method comprises (a) dividing a hardware schedule table into N logical schedule tables which are separated by table delimiters; and (b) assigning an identifier corresponding to a connection in the network in a scheduling table which is one of the N logical schedule tables.

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San Jose, CA, United States of America

Radesh Manian