Intel Corporation

Radek P Chalupa

Christopher J Jezewski

Harsono S Simka

Sadasivan Shankar

Flavio Griggio

Daniel J Zierath

Anand Durairajan

Jiun-Chan Yang

Inane Meric

Iouri Lantassov

Terry T Buckley

Methods/structures of forming substrate tap structures are described. Those methods/structures may include forming a plurality of conductive interconnect structures on an epitaxial layer disposed on a substrate, wherein individual ones of the plurality of conductive interconnect structures are adjacent each other, forming a portion of a seed layer on at least one of the plurality of conductive interconnect structures, and forming a conductive trace on the seed layer.

Methods of forming substrate interconnect structures for enhanced thin seed conduction

A method for an electroplating cell which includes providing an anode chamber with at least two concentric anodes including an inner anode and an outer anode; generating a computer generated model with a simulation computer program; and selecting at least one current ratio from the computer generated model, with the computer generated model having a plurality of current ratios from which the at least one current ratio is selected and the one current ratio being a ratio of an inner electrical current to an outer electrical current. The method further includes applying the inner electrical current to the inner anode and the outer electrical current to the outer anode and adjusting the inner and outer electrical currents to incorporate the one current ratio. The generating of the computer generated model with the simulation computer program includes using a first iterative loop to determine a potential field in the anode chamber.

Apparatus having plating solution container with current applying anodes

Growing community of inventors

Portland, OR, United States of America

Radek P Chalupa