Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Other

Rachid Kadri

George D Megason

John Robert Grady

Stephen F Contreras

Wanda L Bloomfield

David S Blocker

In one example, a mixed signaling socket includes a set of central processing unit (CPU) cores coupled via an inter-core link and a set of analog circuits having an analog input, each analog circuit coupled to a respective CPU core via a separate private bus. A field programmable gate array (FPGA) control circuit is coupled to the inter-core link and the set of analog circuits to provide predicable clock timing to the set of analog circuits and control signals to the set of CPU cores. An analog to digital module in at least one CPU core includes instructions to perform an analog to digital conversion to create a digital representation of the analog input using the predictable clock timing and control signals from the FPGA.

Multi-core circuit with mixed signaling

An example apparatus comprises a first compute node including a first processor; a second compute node including a second processor; an input/manta (I/O) interface to selectively couple the first and second compute nodes to a set of I/O resources; and a voltage regulator including a set of power phase circuits, the voltage regulator to operate in a fault tolerant mode to provide power from selected ones of a first portion of the set of power phase circuits to the first compute node and to provide power from selected ones of a second portion of the set of power phase circuits to the second compute node.

Multiple compute nodes

A method and system are disclosed to reduce trace length and capacitance in a large memory footprint. When more dual in-line memory module (DIMM) connectors are used per memory channel, the overall bus bandwidth may be affected by trace length and trace capacitance. In order to reduce the overall trace length and trace capacitance, the system and method use a palm tree topology placement, i.e., back-to-back DIMM placement, to place surface mount technology (SMT) DIMM connectors (instead of through-hole connectors) back-to-back in a mirror fashion on each side of a printed circuit board (PCB). The system and method may improve signal propagation time when compared to the commonly used traditional topology placements in which all DIMM connectors are placed on one side of the PCB.

Method and system for reducing trace length and capacitance in a large memory footprint

An electronic device includes a housing defining an enclosure, one or more processors in the enclosure, and one or more memory modules in the enclosure. Disk storage drives are provided in an in-line arrangement within the enclosure such that a rear portion of one disk storage drive is adjacent a front portion of another disk storage drive.

Computer including hot-pluggable disk storage drives that are mounted in an in-line arrangement

A finite state electrical automaton modeled after a human neuron comprises a plurality of weighted inputs that pass into a state computing unit. A feedback mechanism changes the weights of the inputs as needed to control the response of the automaton to a desired output. A clock signal allows the automaton to function as a discrete time system. Unlike the threshold gates, the present automaton is capable of outputting an n-bit digital value analogous to a cell membrane potential. Because this automaton is capable of outputting more than two simple states it is a better building block for building neural nets.

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Houston, TX, United States of America

Rachid Kadri