Chartered Semiconductor Manufacturing Ltd (corporation)

Rachel Low

Sung Mun Jung

Dong Kyun Sohn

Siow Lee Chwa

Swee Tuck Woo

Sripad Sheshagiri Nagarad

Xiaoyu Chen

Donghua Liu

Yoke Leng Louis Lim

Louis Lim

Xiao Yu Chen

Dong Hua Liu

A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The access transistor is a hybrid transistor which includes a gate with a thick gate dielectric layer formed on the thin gate well.

Non-volatile memory cell with a hybrid access transistor

In an non-limiting example, we provide a substrate having a cell region, and non-cell regions. We form a tunneling dielectric layer, a charge storing layer, a top insulating layer (e.g., ONO), over the substrate. Then we form a conductive pad layer over the top insulating layer. We form isolation trenches in the pad layer, the charge storing layer and the tunneling dielectric layer and into the substrate. We form isolation regions in the isolation trenches. We remove the pad layer, charge storing layer and the tunneling dielectric layer in the non-cell regions. We form a gate layer over the pad layer and the substrate surface. We complete to form the memory (e.g., SONOS) device in the cell region and other devices in the non-cell regions of the substrate.

Process integration scheme of SONOS technology

Growing community of inventors

Singapore, Singapore

Rachel Low