Imagination Technologies Limited

Rachel Edmonds

Sam Elliott

Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial of degree k in a sub-function p over a set of values of p, k being an integer greater than or equal to one. The methods include: verifying that an instantiation of the hardware design correctly evaluates the sub-function p; formally verifying that an instantiation of the hardware design implements a function that is polynomial of degree k in p by formally verifying that, for all values of p in the set of values of p, an instantiation of the hardware design has a constant kdifference; and verifying that an instantiation of the hardware design generates an expected output in response to each of at least e different values of p in the set of values of p, wherein e is equal to k when a value of the kdifference is predetermined and e is equal to k+1 when the value of the kdifference is not predetermined.

Verification of hardware design for an integrated circuit that implements a function that is polynomial in one or more sub-functions

A hardware design for a component that evaluates a main algebraic expression comprising at least two variables is verified, the main algebraic expression being representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions. An instantiation of the hardware design is verified as correctly evaluating each of the plurality of sub-algebraic expressions, and the instantiation of the hardware design is formally evaluated as correctly evaluating one or more combinations of sub-algebraic expressions, wherein the one or more combinations comprises a combination that is equivalent to the main algebraic expression.

Verification of hardware design for component that evaluates an algebraic expression using decomposition and recombination

Methods and systems for verifying a hardware design for a component that evaluates a main algebraic expression comprising at least two variables wherein the main algebraic expression is representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions. The methods include: for each of the plurality of sub-algebraic expressions, verifying that an instantiation of the hardware design generates a correct output to that sub-algebraic expression for valid values of each variable in that sub-algebraic expression; and for each of one or more combinations of sub-algebraic expressions, formally verifying that an instantiation of the hardware design generates a correct output to that combination by comparing an output of an instantiation of the hardware design under a first set of constraints to an output of an instantiation of the hardware design under a second set of constraints; wherein the one or more combinations comprises a combination that is equivalent to the main algebraic expression.

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Hertfordshire, United Kingdom

Rachel Edmonds