Intel Corporation

Rachael Jade Parker

Martin Spence Denham

David Johnston

Kuan-Yueh Shen

Georgios C Dogiamis

Keng L Wong

Gregory F Taylor

Hon-Mo Raymond Law

Patrick John Ott

Calvin Chiem

Javier Dacuna Santos

Adel A Elsherbini

Feras Eid

Ram K Krishnamurthy

Sanu K Mathew

Nasser A Kurd

Ernie F Brickell

Chee How Lim

Hung-Piao Ma

Edward Paul Osburn

Mark L Neidengard

Kaizad Rumy Mistry

Wenliang Chen

Mohsen Alavi

Gregory M Iovino

Ananda G Sarangi

Stephen M Ramey

Timothy D Low

Paul Gregory Slankard

Jyothi Bhaskarr Velamala

Techniques and mechanisms for facilitating random number generation with an entropy source. In an embodiment, the entropy source comprises two complementary metal-oxide-semiconductor (CMOS) inverters which are cross-coupled with each other between a first node and a second node. A third CMOS inverter of the entropy source includes an output terminal coupled to the first node, and an input terminal which is to receive an adjustment voltage that is based on a first signal at the first node. The first, second and third CMOS inverters are each coupled to a third node by which each is to draw power. The entropy source is to update the first signal based on the adjustment voltage. In another embodiment, the entropy source is coupled to a switched capacitor circuit which is to generate the adjustment voltage based on a feedback of the first signal.

Entropy source and charge pump of a random number generator

A microelectronic assembly is provided, comprising: a first plurality of integrated circuit (IC) dies in a first level, each one of the first plurality of IC dies having respective first physical unclonable function (PUF) circuits; a second IC die having a second PUF circuit and a security circuit; a second plurality of IC dies in a second level, the second level not coplanar with the first level, the first level and the second level being coupled with interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects; and conductive pathways between the first plurality of IC dies and the second IC die for communication between the first PUF circuits and the second PUF circuit, the conductive pathways comprising a portion of the interconnects.

Disaggregated entropy services for microelectronic assemblies

Techniques and mechanisms for providing physically unclonable function (PUF) circuitry at a substrate which supports coupling to an integrated circuit (IC) chip. In an embodiment, the substrate comprises an array of electrodes which extend in a level of metallization at a side of the insulator layer. A cap layer, disposed on the array, is in contact with the electrodes and with a portion of the insulator layer which is between the electrodes. A material of the cap layer has a different composition or microstructure than the metallization. Regions of the cap layer variously provide respective impedances each between a corresponding two electrodes. In other embodiments, the substrate includes (or couples to) integrated circuitry that is operable to determine security information based on the detection of one or more such impedances.

Physically unclonable function circuitry of a package substrate and method of providing same

The disclosure generally provides methods, systems and apparatus for an improved a Physically Unclonable Function (PUF). In one embodiment, the disclosure relates to a method to provide data from a Physically Unclonable Function (PUF) circuit array. The method includes storing a plurality of first data bits into a respective ones of a plurality of first bitcells of the PUF array to form a first dataset; storing a plurality of second data bits into a respective ones of a plurality of second bitcells of the PUF array, the plurality of second data bits defining a helper dataset; reading the first dataset from the plurality of first bitcells to provide a first read dataset; applying an error correction factor to the first read data dataset to form a security key dataset; and outputting the security key dataset from the PUF circuit array.

Method, system and apparatus for error correction coding embedded in physically unclonable function arrays

An apparatus is provided which comprises: a phase detector to receive a reference clock and a feedback clock; and one or more switchable heat elements controllable by an output of the phase detector, wherein the one or more switchable heat elements are coupled to a physically unclonable function circuit.

Supply voltage and temperature insensitive physically unclonable function circuit

Techniques and mechanisms for changing a consistency with which a cell circuit ('cell') settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCl) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCl stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.

Device, system, and method to change a consistency of behavior by a cell circuit

Embodiments include apparatuses, methods, and systems for a random number generator that includes an entropy source. The entropy source may be coupled to a deterministic feedback circuit and a stochastic feedback circuit. The deterministic feedback circuit may include detection logic to detect when a bit of the output signal of the entropy source has registered, a pre-delay feedback path to cause the entropy source to power off responsive to the detection, and a post-delay feedback path to cause the entropy source to power on, after the entropy source is powered off, to generate a second bit of the output signal. The post-delay feedback path may include one or more delay cells that are bypassed by the pre-delay feedback path. Other circuits and techniques related to random number generators are also described. Further embodiments may be described and/or claimed.

Random number generator including entropy source

An IC cell designed to assert one of multiple possible output states, each with equal probability, implemented to assert a pre-determined one of the multiple output states based on random variations within the IC cell, such as random process variations. An array of IC cells is configurable to provide a hardware-embedded key upon power-up that is unique to the combination of random variations of selected IC cells, resistant to tampering prior to and during manufacture, and tolerant to aging, instantaneous thermal noise, and environmental variations, such as voltage and temperature fluctuations. The key may be used as, without limitation, a Platform Root Key, a High-Bandwidth Digital Content Protection (HDCP) key, an Enhanced Privacy Identification (EPID) key, and/or an Advanced Access Content System (AACS) key. Also disclosed are techniques to measure stability and stress-harden an IC cell based on output states of the IC cell.

Hardware-embedded key based on random variations of a stress-hardened inegrated circuit

An integrated circuit includes a programmable logic device and optionally a control circuit coupled to the programmable logic device (PLD). The control circuit may detect that a reconfiguration criterion is satisfied. Responsive to the reconfiguration criterion being satisfied, the control logic may configure, using one or more randomizations, the PLD to implement a secret operation, wherein a first randomized configuration of the PLD results in a first circuit implementation that is different from, but functionally equivalent to, a second circuit implementation that results from a second randomized configuration of the PLD.

Secret operations using reconfigurable logics

A method and system for creating random cryptographic keys in hardware is described. One or more bits are generated via one or more random bit circuits. Each random bit circuit includes a sensing device coupled to a first device and a second device to compare the first device against the second device and to generate a random bit from a random state value. The generated bits from the random bit circuits are read, and a cryptographic key may then be computed based on the generated bits.

Method and system for creating random cryptographic keys in hardware

A JTAG-compatible device includes a unique identifier stored in dedicated non-volatile memory, a test access port (TAP) controller, a TAP instruction register, a dedicated data register, and a comparison block. The TAP instruction register enables and/or disables TAP instruction execution by the device. The dedicated data register is of a length that is the same or a subset of the length of the unique identifier. The comparison block can be an arithmetic logic unit (ALU) or other circuitry that compares a code scanned into the dedicated data register with the unique identifier stored in a PROM. The TAP controller can selectively ignore TAP commands if a code scanned into dedicated data register does not match the stored unique identifier. This allows the TAP controller to conditionally or independently control several devices that are connected in parallel. The unique identifier can be device-specific, device type-specific, and/or device configuration specific.

Method and apparatus for independent control of devices under test connected in parallel

A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.

Growing community of inventors

Forest Grove, OR, United States of America

Rachael Jade Parker