Nec Usa, Inc.

Nec Corporation

Georgia Tech Research Corporation

Rabindra K Roy

Srimat T Chakradhar

Savita Banerjee

Sujit Dey

Abhijit Chatterjee

Miodrag Potkonjak

Toshinobu Ono

A synchronous test model (STM) and corresponding method capture the essential behavior of an asynchronous circuit under test. During operation of the method, (1) An STM for the asynchronous circuit is constructed assuming either a user-specified cycle length or an estimated cycle length; (2) a target fault list is created containing only faults in the asynchronous circuit, (3) test patterns are generated from the STM using a synchronous test generator; (4) the test patterns are translated into test sequences for the asynchronous circuit; and (5) the translated patterns are validated by fault simulation on the asynchronous circuit. The STM offers numerous advantages over prior art methods namely, (1) synchronous, sequential test generation techniques can be used to generate tests for the model, (2) tests generated for the STM can always be translated into tests for the asynchronous circuit under test, and (3) these tests will not suffer from test invalidation due to unstable states, because the STM enforces a fundamental mode of operation during test generation. Experimental results on several benchmarks show that the STM method generates high fault coverage tests with no test invalidation.

Method for testing asynchronous circuits

Low power linear digital signal processing circuits are fabricated based on a design synthesis process using activity metrics. The average activity value .theta..sub.i of all the input nodes of the circuit is determined. Architectural transformations of the circuit are performed in order to minimize the average activity value over all the nodes. The transformation resulting in the minimum activity value is the synthesized design used as the basis for fabricating a low power linear digital signal processing circuit.

Synthesis of low power linear digital signal processing circuits using

A method for performing high level synthesis of integrated circuits simultaneously considers testability and resource utilization. The method considers the relationship between hardware sharing, loops in the synthesized data path, and partial scan testing overhead. Hardware sharing is used to minimize the quantity of scan registers required to synthesize data paths with a minimal quantity of loops. A random walk based algorithm is used to break all control data flow graph (CDFG) loops with a minimal quantity of scan registers. Subsequent scheduling and assignment avoids the formation of loops in the data path by reusing the scan registers, while ensuring high resource utilization of the components of hardware costs: execution units, registers and interconnects. The partial scan overhead incurred is less than that of conventional gate level design partial scan techniques.

High level synthesis for partial scan testing

A method of selecting circuit elements in a sequential circuit for partial scan testing relies upon analyzing and breaking reconvergence through the selected circuit element. Different types of reconvergences present in the circuit and their affect on the circuit testability are considered. Harmful reconvergence present in the circuit are broken by scanning a memory element present in the reconvergence path.

Partial scan testability utilizing reconvergence through sequential

A method of asynchronous circuit synthesis of initializable circuits from signal transition graphs (STG) that are either functionally initializable or functionally uninitializable is described. For functionally initializable cases, an initializable implementation can be achieved by proper assignment of don't care values. If the STG is not functionally initializable, the sources of uninitializability in the STG are identified and the STG is transformed into a functionally initializable specification by exploiting concurrency. Initializability is achieved at the expense of minimal removal of concurrency. Moreover, the transformation does not violate liveness and unique state coding properties of the STG. When the STG is functionally initializable or after an uninitializable STG is transformed to become functionally initializable the result is an initializable circuit design.

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Plainsboro, NJ, United States of America

Rabindra K Roy