Mellanox Technologies, Ltd.

Rabie Loulou

Liran Liss

Omri Kahalon

Aviad Shaul Yehezkel

Gal Shalom

Oren Duer

Adi Merav Horowitz

Maxim Gurtovoy

Sami Salloum

Wasim Abu Moch

Methods and systems provided herein involve extracting an input/output (I/O) operation from a packet received over an I/O pipeline, the I/O operation comprising either a read request to read data from at least one storage device or a write request to write data to the at least one storage device; determining that an address associated with the I/O operation exists in a lookup table that is provided for thin provisioning of the at least one storage device; performing one or more RAID calculations associated with the at least one storage device based on the address and the I/O operation; and accessing the at least one storage device to perform the I/O operation based on the one or more RAID calculations; and second processing component configured to carry out a second set of operations that occur when the address associated with the I/O operation does not exist in the lookup table.

Methods and systems for inter-stack communication for logical volume management

API in conjunction with a bridge chip and first and second hosts having first and second memories respectively. The bridge chip connects the memories. The API comprises key identifier registration functionality to register a key identifier for each of plural computer processes performed by the first host, thereby to define plural key identifiers; and/or access control functionality to provide at least computer process Pperformed by the first host with access, typically via the bridge chip, to at least local memory buffer Mresiding in the second memory, typically after the access control functionality first validates that process Phas a key identifier which has been registered, e.g., via the key identifier registration functionality. Typically, the access control functionality also prevents at least computer process P, performed by the first host, which has not registered a key identifier, from accessing local memory buffer M, e.g., via the bridge chip.

System which provides plural processes in a host with asynchronous access to plural portions of the memory of another host

A connector module includes a signal interface, a wireless communication module and a connector housing. The signal interface is configured to exchange signals between a cable and a communication unit when the connector module is connected to the communication unit. The wireless communication module is configured to exchange information in a first mode between the communication unit and a wireless terminal when the connector module is connected to the communication unit, and, when the connector module is disconnected from the communication unit, to exchange information in a second between a memory internal to the connector module and the wireless terminal mode. The connector housing contains the signal interface and the wireless communication module.

Connector module with internal wireless communication device

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Nazareth, Israel

Rabie Loulou