Texas Instruments Corporation

Rabah Mezenner

Cetin Kaya

Richard Lee Knipe

Anthony DiCarlo

Wayland B Holland

James D Huffman

Patrick Ian Oden

Henry C Chu

James Carl Baker

Rodney Dean Miller

Douglas A Webb

Richard O Gale, Jr

Cuiling Gong

Randy Long

Mark Andrew Franklin

Harlan Paul Cleveland

George Nicholas Harakas

Stanford Joseph Gautier, Jr

In accordance with the teachings of the present disclosure, methods and apparatus are provided for a semiconductor device having thin anti-reflective layer(s) operable to absorb radiation that may otherwise reflect off surfaces disposed inwardly from the anti-reflective layer(s). In a method embodiment, a method for manufacturing a semiconductor device includes forming a support structure outwardly from a substrate. The support structure has a first thickness and a first outer sidewall surface that is not parallel with the substrate. The first outer sidewall surface has a first minimum refractive index. The method further includes forming an anti-reflective layer outwardly from the first outer sidewall surface. The anti-reflective layer has: a second outer sidewall surface that is not parallel with the substrate, a second refractive index that is greater than the first minimum refractive index, and a second thickness that is less than the first thickness.

Methods and apparatus for manufacturing semiconductor devices

A reflective and deformable micromirror device comprises a reflective micromirror plate attached to a deformable hinge that is formed on and held by a hinge post on a substrate. The substrate has an addressing electrode formed thereon. A selected dielectric material is disposed between the deformable hinge and the addressing electrode.

Micromirror device and a method of making the same

A micromirror arrayfabricated on a semiconductor substrate. The arrayis comprised of three operating layers. An addressing layeris fabricated on the substrate. A hinge layeris spaced above the addressing layerby an air gap. A mirror layeris spaced over the hinge layerby a second air gap. The hinge layerhas a hingeunder and attached to the mirror, the hingepermitting the mirrorto tilt. The hinge layerfurther has spring tipsunder the mirror, which are attached to the addressing layer. These spring tipsprovide a stationary landing surface for the mirror

Yokeless hidden hinge digital micromirror device

As robust hinge post structure for use with torsional hinged devices such as micromirrors and method of manufacturing is disclosed. The fabrication process uses a protective layer such as BARC on the bottom of the aperture used to form the hinge post structure to protect an oxide layer during an etching step. The oxide layer, in turn protects the metal layer at the bottom of the aperture. Therefore, the metal layer, the oxide layer, and the protective layer prevent the erosion and/or pitting of the bottom electrode during a cleaning process, and provide additional support to the structure.

Utilizing a protective plug to maintain the integrity of the FTP shrink hinge

A micromirror array fabricated on a semiconductor substrate. The array is comprised of three operating layers. An addressing layer is fabricated on the substrate. A hinge layer is spaced above the addressing layer by an air gap. A mirror layer is spaced over the hinge layer by a second air gap. The hinge layer has a hinge under and attached to the mirror, the hinge permitting the mirror to tilt. The hinge layer further has spring tips under the mirror, which are attached to the addressing layer. These spring tips provide a stationary landing surface for the mirror.

MEMS device deflection stop

According to one embodiment of the present invention a micro-mirror element comprises a lower layer, a first middle layer, a second middle layer, and a micro-mirror. The lower layer includes an address portion for receiving an address voltage and a bias portion for receiving a bias voltage respectively. The first middle layer is electrically coupled to the bias portion of the lower layer. The second middle layer is electrically coupled to the first middle layer. The micro-mirror is coupled to the second middle layer and comprises a reflective surface operable to selectively tilt, in response to an application of a bias voltage and an address voltage to the lower layer, to reflect a beam of light.

Micro-mirror element with double binge

A method of fabricating improved vias in a multilayer MEMS device. Via seats are patterned into first layer, such that each via will have a via seat at the bottom of the via opening. The via openings are then patterned into a second layer. A third layer of material is deposited, such that the material at least partly fills the via opening and the via seat. The material forms a support post that is anchored to the first layer by means of the material in the via seat.

Via adhesion in multilayer MEMS structure

A method of resetting the mirrors (11, 21) of the mirror elements of a digital micro-mechanical device (DMD) (10, 20). A bias voltage is applied to the mirror elements and the surface upon which they land, but is removed after the address voltage has been switched. (FIG. 4). Immediately before the bias is removed, a reset voltage is added to the bias voltage. The reset voltage signal is comprised of a number of pulses at a frequency that matches the resonant frequency of the mirrors. The magnitude of the reset voltage results in a total applied voltage that permits vibrational energy to build but that is insufficient to cause the mirrors to become unstuck until the end of the reset signal. In other words, the magnitude of the reset voltage is small relative to that of the bias voltage.

Phase matched reset for digital micro-mirror device

A method of providing control signals for resetting mirror elements (10,20) of a digital micro-mirror device (DMD) having reset groups (FIG. 4), or for resetting moveable elements of other micro-mechanical devices that operate with similar principles. A bias voltage is applied to the mirrors and their landing sites, and an address voltage is applied under the mirrors. (FIG. 3). The address voltage is held at an intermediate level except during a reset period. During this reset period, the address voltage is increased. Also, during reset, the bias applied to mirrors to be reset is pulsed and offset, and the bias applied to mirrors not to be reset is increased. (FIGS. 5 and 6).

Switched control signals for digital micro-mirror device with split reset

The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10). The method of this invention increases compaction gate-current efficiency by reverse biasing the source (11)/substrate (23) junction of the cell being programmed. The reverse biasing is accomplished, for example, by applying a bias voltage to the source (11) or by placing a diode (27), a resistor (29) or other impedance in series with the source (11). The reverse biasing limits the source current (Is) of cell being programmed and of the entire array during flash-programming compaction.

Method of using source bias to raise threshold voltages and/or to

The erasing method of this invention results in a relatively narrow distribution of threshold voltages when used to flash erase a group of floating-gate-type memory cells (10). Each cell includes a control gate (14), a source (11) and a drain (12). The method comprises connecting the control gates (14) to a control-gate voltage (Vg), connecting the sources (11) to a source voltage (Vs) having a higher potential than the control-gate voltage (Vg) and connecting the drains (12) to a drain subcircuit (DS) having, in at least one embodiment, a potential (Vd) between the control-gate voltage (Vg) and the source voltage (Vs), the drain subcircuit (DS) having a sufficiently low impedance to allow current flow between the sources (11) and drains (12) at a time during the erasing operation. The drain subcircuit (DS) allows for optimum threshold voltage distribution and a part of the drain potential (Vd) may be fed back to arrest the erase process at an optimum point.

Biasing circuit and method to achieve compaction and self-limiting erase

The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10). The method of this invention increases compaction gate-current efficiency by reverse biasing the source (11)/substrate (23) junction of the cell being programmed. The reverse biasing is accomplished, for example, by applying a bias voltage to the source (11 ) or by placing a diode (27), a resistor (29) or other impedance in series with the source (11). The reverse biasing limits the source current (Is) of cell being programmed and of the entire array during flash-programming compaction.

Method of using source bias to increase threshold voltages and/or to

The erasing method of this invention results in a relatively narrow distribution of threshold voltages when used to flash erase a group of floating-gate-type memory cells (10). Each cell includes a control gate (14), a source (11 ) and a drain (12). The method comprises connecting the control gates (14) to a control-gate voltage (Vg), connecting the sources (11 ) to a source voltage (Vs) having a higher potential than the, control-gate voltage (Vg) and connecting the drains (12) to a drain subcircuit (DS) having, in at least one embodiment, a potential (Vd) between the control-gate voltage (Vg) and the source voltage (Vs), the drain subcircuit (DS) having a sufficiently low impedance to allow current flow between the sources (11) and drains (12) at a time during the erasing operation. The drain subcircuit (DS) allows for optimum threshold voltage distribution and a part of the drain potential (Vd) may be fed back to arrest the erase process at an optimum point.

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Richardson, TX, United States of America

Rabah Mezenner